linux-kernel - Re: (subset) [PATCH v7 0/7] Add Aspeed G7 gpio support

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Message-ID: <172839616610.55104.2573120540182552334.b4-ty@linaro.org>
Date: Tue,  8 Oct 2024 16:02:52 +0200
From: Bartosz Golaszewski <brgl@...ev.pl>
To: linus.walleij@...aro.org,
	brgl@...ev.pl,
	robh@...nel.org,
	krzk+dt@...nel.org,
	conor+dt@...nel.org,
	joel@....id.au,
	andrew@...econstruct.com.au,
	linux-gpio@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-aspeed@...ts.ozlabs.org,
	linux-kernel@...r.kernel.org,
	BMC-SW@...eedtech.com,
	Peter.Yin@...ntatw.com,
	Jay_Zhang@...ynn.com,
	Billy Tsai <billy_tsai@...eedtech.com>
Cc: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
Subject: Re: (subset) [PATCH v7 0/7] Add Aspeed G7 gpio support

From: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>


On Tue, 08 Oct 2024 16:14:43 +0800, Billy Tsai wrote:
> The Aspeed 7th generation SoC features two GPIO controllers: one with 12
> GPIO pins and another with 216 GPIO pins. The main difference from the
> previous generation is that the control logic has been updated to support
> per-pin control, allowing each pin to have its own 32-bit register for
> configuring value, direction, interrupt type, and more.
> This patch serial also add low-level operations (llops) to abstract the
> register access for GPIO registers and the coprocessor request/release in
> gpio-aspeed.c making it easier to extend the driver to support different
> hardware register layouts.
> 
> [...]

Applied, thanks!

[1/7] gpio: aspeed: Add the flush write to ensure the write complete.
      commit: 1bb5a99e1f3fd27accb804aa0443a789161f843c
[2/7] gpio: aspeed: Use devm_clk api to manage clock source
      commit: a6191a3d18119184237f4ee600039081ad992320

Best regards,
-- 
Bartosz Golaszewski <bartosz.golaszewski@...aro.org>