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Message-Id: <960826e94a94c1c0a25261e4081de7fa82dff5f5.1728355974.git.unicorn_wang@outlook.com>
Date: Tue, 8 Oct 2024 11:04:33 +0800
From: Chen Wang <unicornxw@...il.com>
To: ukleinek@...nel.org,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
unicorn_wang@...look.com,
inochiama@...look.com,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-pwm@...r.kernel.org,
linux-riscv@...ts.infradead.org,
chao.wei@...hgo.com,
haijiao.liu@...hgo.com,
xiaoguang.xing@...hgo.com,
chunzhi.lin@...hgo.com
Subject: [PATCH v3 3/3] riscv: sophgo: dts: add pwm controller for SG2042 SoC
From: Chen Wang <unicorn_wang@...look.com>
SG2042 has one PWM controller, which has 4 pwm output channels.
Signed-off-by: Chen Wang <unicorn_wang@...look.com>
---
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index 4e5fa6591623..048792b30617 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -165,6 +165,14 @@ port2a: gpio-controller@0 {
};
};
+ pwm: pwm@...000c000 {
+ compatible = "sophgo,sg2042-pwm";
+ reg = <0x70 0x3000c000 0x0 0x20>;
+ #pwm-cells = <2>;
+ clocks = <&clkgen GATE_CLK_APB_PWM>;
+ clock-names = "apb";
+ };
+
pllclk: clock-controller@...00100c0 {
compatible = "sophgo,sg2042-pll";
reg = <0x70 0x300100c0 0x0 0x40>;
--
2.34.1
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