linux-kernel - [PATCH v5 6/7] PCI: qcom: Fix the ops for X1E80100 and SC8280X family SoC

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Message-Id: <20241009091540.1446-7-quic_qianyu@quicinc.com>
Date: Wed,  9 Oct 2024 02:15:39 -0700
From: Qiang Yu <quic_qianyu@...cinc.com>
To: manivannan.sadhasivam@...aro.org, vkoul@...nel.org, kishon@...nel.org,
        robh@...nel.org, andersson@...nel.org, konradybcio@...nel.org,
        krzk+dt@...nel.org, conor+dt@...nel.org, mturquette@...libre.com,
        sboyd@...nel.org, abel.vesa@...aro.org, quic_msarkar@...cinc.com,
        quic_devipriy@...cinc.com
Cc: dmitry.baryshkov@...aro.org, kw@...ux.com, lpieralisi@...nel.org,
        neil.armstrong@...aro.org, linux-arm-msm@...r.kernel.org,
        linux-phy@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
        linux-clk@...r.kernel.org, Qiang Yu <quic_qianyu@...cinc.com>
Subject: [PATCH v5 6/7] PCI: qcom: Fix the ops for X1E80100 and SC8280X family SoC

On X1E80100 and SC8280X family SoC, PCIe controllers are connected to
SMMUv3, hence they don't need the config_sid() callback in ops_1_9_0
struct. Fix it by introducing a new ops struct, namely ops_1_21_0, so
that BDF2SID mapping won't be configured during init.

In addition, since it is recommended to disable ASPM L0s on X1E80100 as
same as SC8280X, hence X1E80100 can simply reuse cfg_sc8280xp as its
config.

Signed-off-by: Qiang Yu <quic_qianyu@...cinc.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 88a98be930e3..c533e6024ba2 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1367,6 +1367,16 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
 	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
 };
 
+/* Qcom IP rev.: 1.21.0 */
+static const struct qcom_pcie_ops ops_1_21_0 = {
+	.get_resources = qcom_pcie_get_resources_2_7_0,
+	.init = qcom_pcie_init_2_7_0,
+	.post_init = qcom_pcie_post_init_2_7_0,
+	.host_post_init = qcom_pcie_host_post_init_2_7_0,
+	.deinit = qcom_pcie_deinit_2_7_0,
+	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
+};
+
 static const struct qcom_pcie_cfg cfg_1_0_0 = {
 	.ops = &ops_1_0_0,
 };
@@ -1405,7 +1415,7 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
 };
 
 static const struct qcom_pcie_cfg cfg_sc8280xp = {
-	.ops = &ops_1_9_0,
+	.ops = &ops_1_21_0,
 	.no_l0s = true,
 };
 
@@ -1837,7 +1847,7 @@ static const struct of_device_id qcom_pcie_match[] = {
 	{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
 	{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
 	{ .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
-	{ .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp },
 	{ }
 };
 
-- 
2.34.1