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Message-ID: <20241009095556.1754876-6-quic_jiegan@quicinc.com>
Date: Wed, 9 Oct 2024 17:55:56 +0800
From: Jie Gan <quic_jiegan@...cinc.com>
To: Suzuki K Poulose <suzuki.poulose@....com>,
Mike Leach
<mike.leach@...aro.org>,
James Clark <james.clark@...aro.org>,
"Alexander
Shishkin" <alexander.shishkin@...ux.intel.com>,
Maxime Coquelin
<mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>
CC: Jinlong Mao <quic_jinlmao@...cinc.com>, <coresight@...ts.linaro.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<devicetree@...r.kernel.org>,
Tingwei Zhang <quic_tingweiz@...cinc.com>,
Yuanfang Zhang <quic_yuanfang@...cinc.com>,
Tao Zhang
<quic_taozha@...cinc.com>,
Song Chai <quic_songchai@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>
Subject: [PATCH v5 RESEND 5/5] arm64: dts: qcom: Add CTCU and ETR nodes for SA8775p
Add CTCU and ETR nodes in DT to enable related functions.
Signed-off-by: Jie Gan <quic_jiegan@...cinc.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 160 ++++++++++++++++++++++++++
1 file changed, 160 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 23f1b2e5e624..a8b509495440 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -1664,6 +1664,35 @@ ice: crypto@...8000 {
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
+ ctcu@...1000 {
+ compatible = "qcom,sa8775p-ctcu";
+ reg = <0x0 0x4001000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ ctcu_in0: endpoint {
+ remote-endpoint =
+ <&etr0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ctcu_in1: endpoint {
+ remote-endpoint =
+ <&etr1_out>;
+ };
+ };
+ };
+ };
+
stm: stm@...2000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x4002000 0x0 0x1000>,
@@ -1867,6 +1896,129 @@ qdss_funnel_in1: endpoint {
};
};
+ replicator@...6000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x4046000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ qdss_rep_out0: endpoint {
+ remote-endpoint =
+ <&etr_rep_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ qdss_rep_in: endpoint {
+ remote-endpoint =
+ <&swao_rep_out0>;
+ };
+ };
+ };
+ };
+
+ tmc_etr: tmc@...8000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x4048000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ iommus = <&apps_smmu 0x04c0 0x00>;
+
+ arm,scatter-gather;
+
+ out-ports {
+ port {
+ etr0_out: endpoint {
+ remote-endpoint =
+ <&ctcu_in0>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ etr0_in: endpoint {
+ remote-endpoint =
+ <&etr_rep_out0>;
+ };
+ };
+ };
+ };
+
+ replicator@...e000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x404e000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ etr_rep_out0: endpoint {
+ remote-endpoint =
+ <&etr0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ etr_rep_out1: endpoint {
+ remote-endpoint =
+ <&etr1_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ etr_rep_in: endpoint {
+ remote-endpoint =
+ <&qdss_rep_out0>;
+ };
+ };
+ };
+ };
+
+ tmc_etr1: tmc@...f000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x404f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ iommus = <&apps_smmu 0x04a0 0x40>;
+
+ arm,scatter-gather;
+ arm,buffer-size = <0x400000>;
+
+ out-ports {
+ port {
+ etr1_out: endpoint {
+ remote-endpoint =
+ <&ctcu_in1>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ etr1_in: endpoint {
+ remote-endpoint =
+ <&etr_rep_out1>;
+ };
+ };
+ };
+ };
+
funnel@...4000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x4b04000 0x0 0x1000>;
@@ -1942,6 +2094,14 @@ out-ports {
#address-cells = <1>;
#size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ swao_rep_out0: endpoint {
+ remote-endpoint =
+ <&qdss_rep_in>;
+ };
+ };
+
port@1 {
reg = <1>;
swao_rep_out1: endpoint {
--
2.34.1
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