linux-kernel - Re: [PATCH 2/4] arm64: dts: qcom: x1e80100: Describe the SDHC controllers

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Message-ID: <ZwZZalFKXiQh0BAK@linaro.org>
Date: Wed, 9 Oct 2024 13:22:34 +0300
From: Abel Vesa <abel.vesa@...aro.org>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: Ulf Hansson <ulf.hansson@...aro.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Bjorn Andersson <andersson@...nel.org>,
	Konrad Dybcio <konradybcio@...nel.org>,
	Johan Hovold <johan@...nel.org>,
	Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
	linux-mmc@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH 2/4] arm64: dts: qcom: x1e80100: Describe the SDHC
 controllers

On 24-10-09 08:49:03, Krzysztof Kozlowski wrote:
> On Tue, Oct 08, 2024 at 05:05:56PM +0300, Abel Vesa wrote:
> > Describe the two SHDC v5 controllers found on x1e80100 platform.
> > 
> > Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> > ---
> >  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 108 +++++++++++++++++++++++++++++++++
> >  1 file changed, 108 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > index a36076e3c56b5b8815eb41ec55e2e1e5bd878201..b835fd87b977ae81f687c4ea15f6f2f89e02e9b1 100644
> > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > @@ -3880,6 +3880,114 @@ lpass_lpicx_noc: interconnect@...0000 {
> >  			#interconnect-cells = <2>;
> >  		};
> >  
> > +		sdhc_2: mmc@...4000 {
> > +			compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
> > +			reg = <0 0x08804000 0 0x1000>;
> > +
> > +			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-names = "hc_irq", "pwr_irq";
> > +
> > +			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
> > +				 <&gcc GCC_SDCC2_APPS_CLK>,
> > +				 <&rpmhcc RPMH_CXO_CLK>;
> > +			clock-names = "iface", "core", "xo";
> > +			iommus = <&apps_smmu 0x520 0>;
> > +			qcom,dll-config = <0x0007642c>;
> > +			qcom,ddr-config = <0x80040868>;
> > +			power-domains = <&rpmhpd RPMHPD_CX>;
> > +			operating-points-v2 = <&sdhc2_opp_table>;
> > +
> > +			interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
> > +					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
> > +			interconnect-names = "sdhc-ddr", "cpu-sdhc";
> > +			bus-width = <4>;
> > +			dma-coherent;
> > +
> > +			/* Forbid SDR104/SDR50 - broken hw! */
> 
> Is it still valid or was it just copied from old code?

So when I did the bring-up of this controller, for some reason I thought
this was needed. But I guess that's not the case since I get this
without it:

[    5.168918] mmc0: new ultra high speed SDR104 SDHC card at address

So will drop in the next version.

Keep in mind that I have no way to test the sdhc_4, so I'll drop it from
there as well.

> 
> > +			sdhci-caps-mask = <0x3 0>;
> 
> Best regards,
> Krzysztof
> 

Thanks for reviewing.

Abel