linux-kernel - [PATCH v10 3/3] dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent

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Message-ID: <20241011140043.1250030-4-daire.mcnamara@microchip.com>
Date: Fri, 11 Oct 2024 15:00:43 +0100
From: <daire.mcnamara@...rochip.com>
To: <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>
CC: <conor.dooley@...rochip.com>, <lpieralisi@...nel.org>, <kw@...ux.com>,
	<robh@...nel.org>, <bhelgaas@...gle.com>, <linux-kernel@...r.kernel.org>,
	<linux-riscv@...ts.infradead.org>, <krzk+dt@...nel.org>,
	<conor+dt@...nel.org>, <daire.mcnamara@...rochip.com>,
	<ilpo.jarvinen@...ux.intel.com>, <kevin.xie@...rfivetech.com>
Subject: [PATCH v10 3/3] dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent

From: Conor Dooley <conor.dooley@...rochip.com>

PolarFire SoC may be configured in a way that requires non-coherent DMA
handling. On RISC-V, buses are coherent by default & the dma-noncoherent
property is required to denote buses or devices that are non-coherent.

Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
Signed-off-by: Daire McNamara <daire.mcnamara@...rochip.com>
Acked-by: Rob Herring <robh@...nel.org>
---
 Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
index 612633ba59e2..5f5f2b25d797 100644
--- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
@@ -44,6 +44,8 @@ properties:
     items:
       pattern: '^fic[0-3]$'
 
+  dma-coherent: true
+
   ranges:
     minItems: 1
     maxItems: 3
-- 
2.43.0