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Message-ID:
<ZQ0PR01MB1253A79F75863E263B24F1689F792@ZQ0PR01MB1253.CHNPR01.prod.partner.outlook.cn>
Date: Fri, 11 Oct 2024 10:43:20 +0000
From: William Qiu <william.qiu@...rfivetech.com>
To: Uwe Kleine-König <u.kleine-koenig@...libre.com>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-pwm@...r.kernel.org" <linux-pwm@...r.kernel.org>, Hal Feng
<hal.feng@...rfivetech.com>, Philipp Zabel <p.zabel@...gutronix.de>
Subject: RE: [PATCH v15] pwm: opencores: Add PWM driver support
> -----Original Message-----
> From: Uwe Kleine-König <u.kleine-koenig@...libre.com>
> Sent: 2024年10月9日 16:11
> To: William Qiu <william.qiu@...rfivetech.com>
> Cc: linux-kernel@...r.kernel.org; linux-pwm@...r.kernel.org; Hal Feng
> <hal.feng@...rfivetech.com>; Philipp Zabel <p.zabel@...gutronix.de>
> Subject: Re: [PATCH v15] pwm: opencores: Add PWM driver support
>
> Hello William,
>
> On Sat, Sep 14, 2024 at 05:51:14PM +0800, William Qiu wrote:
> > diff --git a/drivers/pwm/pwm-ocores.c b/drivers/pwm/pwm-ocores.c new
> > file mode 100644 index 000000000000..d0161b9379d1
> > --- /dev/null
> > +++ b/drivers/pwm/pwm-ocores.c
> > @@ -0,0 +1,241 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * OpenCores PWM Driver
> > + *
> > + * https://opencores.org/projects/ptc
> > + *
> > + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd.
> > + *
> > + * Limitations:
> > + * - The hardware only supports inverted polarity.
> > + * - The hardware minimum period / duty_cycle is (1 / pwm_apb clock
> frequency).
> > + * - The hardware maximum period / duty_cycle is (U32_MAX / pwm_apb
> clock frequency).
> > + * - The output is set to a low level immediately when disabled.
>
> Huh, that's a 100% relative duty cycle. But fine, that gives the opportunity to
> find bugs in consumer drivers. :-)
>
> > + * - When configuration changes are done, they get active immediately
> without resetting
> > + * the counter. This might result in one period affected by both old and
> new settings.
> > + */
> > +
> > [...]
> > +static inline void ocores_pwm_writel(struct ocores_pwm_device *ddata,
> > + unsigned int channel,
> > + unsigned int offset, u32 val)
> > [...]
> > +static inline struct ocores_pwm_device *chip_to_ocores(struct
> > +pwm_chip *chip)
> > [...]
> > +static void __iomem *starfive_get_ch_base(void __iomem *base,
> > + unsigned int channel)
>
> Would be great if all functions had the same prefix. This simplifies debugging
> with tracing, because you can just enable traces for "ocores_pwm_*".
>
Will update.
> > [...]
> > +static int ocores_pwm_apply(struct pwm_chip *chip,
> > + struct pwm_device *pwm,
> > + const struct pwm_state *state) {
> > + struct ocores_pwm_device *ddata = chip_to_ocores(chip);
> > + u32 ctrl_data = 0;
> > + u64 period_data, duty_data;
> > +
> > + if (state->polarity != PWM_POLARITY_INVERSED)
> > + return -EINVAL;
> > +
> > + period_data = mul_u64_u32_div(state->period, ddata->clk_rate,
> NSEC_PER_SEC);
> > + if (!period_data)
> > + return -EINVAL;
> > +
> > + if (period_data > U32_MAX)
> > + period_data = U32_MAX;
> > +
> > + ocores_pwm_writel(ddata, pwm->hwpwm, REG_OCPWM_LRC,
> > +(u32)period_data);
>
> The cast isn't needed.
>
Will drop
> > + duty_data = mul_u64_u32_div(state->duty_cycle, ddata->clk_rate,
> NSEC_PER_SEC);
> > + if (!duty_data)
> > + return -EINVAL;
> > +
> > + if (duty_data > U32_MAX)
> > + duty_data = U32_MAX;
> > +
> > + ocores_pwm_writel(ddata, pwm->hwpwm, REG_OCPWM_HRC,
> (u32)duty_data);
>
> ditto.
>
...
> > + ctrl_data = ocores_pwm_readl(ddata, pwm->hwpwm,
> REG_OCPWM_CTRL);
> > + if (state->enabled)
> > + ocores_pwm_writel(ddata, pwm->hwpwm, REG_OCPWM_CTRL,
> > + ctrl_data | REG_OCPWM_CNTR_EN |
> REG_OCPWM_CNTR_OE);
> > + else
> > + ocores_pwm_writel(ddata, pwm->hwpwm, REG_OCPWM_CTRL,
> > + ctrl_data & ~(REG_OCPWM_CNTR_EN |
> REG_OCPWM_CNTR_OE));
>
> If you're clearing REG_OCPWM_CNTR_OE (Output Enable?), does the output
> really go low? Or is that due to an external pull down on your board?
>
The output will really go low.
> > +
> > + return 0;
> > +}
> > [...]
> > +static int ocores_pwm_probe(struct platform_device *pdev) {
> > + const struct of_device_id *id;
> > + struct device *dev = &pdev->dev;
> > + struct ocores_pwm_device *ddata;
> > + struct pwm_chip *chip;
> > + struct clk *clk;
> > + struct reset_control *rst;
> > + int ret;
> > +
> > + id = of_match_device(ocores_pwm_of_match, dev);
> > + if (!id)
> > + return -EINVAL;
>
> Error message here? Better use device_get_match_data() here. Then you don't
> need the of-specific headers (IIUC).
>
Will update.
> > + chip = devm_pwmchip_alloc(&pdev->dev, 8, sizeof(*ddata));
> > + if (IS_ERR(chip))
> > + return -ENOMEM;
> > +
> > + ddata = chip_to_ocores(chip);
> > + ddata->data = id->data;
> > + chip->ops = &ocores_pwm_ops;
> > +
> > + ddata->regs = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(ddata->regs))
> > + return dev_err_probe(dev, PTR_ERR(ddata->regs),
> > + "Unable to map IO resources\n");
> > +
> > + clk = devm_clk_get_enabled(dev, NULL);
> > + if (IS_ERR(clk))
> > + return dev_err_probe(dev, PTR_ERR(clk),
> > + "Unable to get pwm's clock\n");
> > +
> > + ret = devm_clk_rate_exclusive_get(dev, clk);
> > + if (ret)
> > + return ret;
> > +
> > + rst = devm_reset_control_get_optional_exclusive(dev, NULL);
> > + if (IS_ERR(rst))
> > + return dev_err_probe(dev, PTR_ERR(rst),
> > + "Unable to get pwm's reset\n");
> > +
> > + ret = reset_control_deassert(rst);
> > + if (ret)
> > + return ret;
> > +
> > + ret = devm_add_action_or_reset(dev, ocores_pwm_reset_control_assert,
> rst);
> > + if (ret)
> > + return ret;
>
> If you respin anyhow, switch to
> devm_reset_control_get_optional_exclusive_deasserted(). Up to now this only
> exists in next, but I'd care to apply this is a way that doesn't fail to build then.
>
Will update.
> > + ddata->clk_rate = clk_get_rate(clk);
> > + if (ddata->clk_rate > NSEC_PER_SEC)
> > + return -EINVAL;
> > +
> > + ret = devm_pwmchip_add(dev, chip);
> > + if (ret < 0)
> > + return dev_err_probe(dev, ret, "Could not register PWM chip\n");
> > +
> > + return 0;
> > +}
>
> Best regards
> Uwe
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