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Message-ID: <8161ce3f9c874539195c53feb34a5cee421abf96.camel@intel.com>
Date: Fri, 11 Oct 2024 02:04:38 +0000
From: "Zhang, Rui" <rui.zhang@...el.com>
To: "Hansen, Dave" <dave.hansen@...el.com>, "rafael@...nel.org"
	<rafael@...nel.org>
CC: "Luck, Tony" <tony.luck@...el.com>, "dave.hansen@...ux.intel.com"
	<dave.hansen@...ux.intel.com>, "stable@...r.kernel.org"
	<stable@...r.kernel.org>, "Wysocki, Rafael J" <rafael.j.wysocki@...el.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"mingo@...hat.com" <mingo@...hat.com>, "thorsten.blum@...lux.com"
	<thorsten.blum@...lux.com>, "tglx@...utronix.de" <tglx@...utronix.de>,
	"yuntao.wang@...ux.dev" <yuntao.wang@...ux.dev>, "hpa@...or.com"
	<hpa@...or.com>, "peterz@...radead.org" <peterz@...radead.org>,
	"bp@...en8.de" <bp@...en8.de>, "linux-pm@...r.kernel.org"
	<linux-pm@...r.kernel.org>, "Brown, Len" <len.brown@...el.com>, "Pandruvada,
 Srinivas" <srinivas.pandruvada@...el.com>, "x86@...nel.org" <x86@...nel.org>
Subject: Re: [PATCH V2] x86/apic: Stop the TSC Deadline timer during lapic
 timer shutdown

Hi, Dave,

On Thu, 2024-10-10 at 17:43 -0700, Dave Hansen wrote:
> How about something like the completely untested attached patch?
> 
> IMNHO, it improves on what was posted here because it draws a
> parallel
> with an AMD erratum and also avoids writes to APIC_TMICT that would
> get
> ignored anyway.

Thanks a lot for the rewrite. The patch looks great to me.

I will test it on our test boxes to make sure skipping the APIC_TMICT
write in TSC deadline mode does not bring unexpected impact to the old
machines.

thanks,
rui

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