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Message-ID: <20241011214353.1625057-3-jmattson@google.com>
Date: Fri, 11 Oct 2024 14:43:51 -0700
From: Jim Mattson <jmattson@...gle.com>
To: kvm@...r.kernel.org
Cc: bp@...en8.de, dave.hansen@...ux.intel.com, hpa@...or.com,
jpoimboe@...nel.org, kai.huang@...el.com, linux-kernel@...r.kernel.org,
mingo@...hat.com, pawan.kumar.gupta@...ux.intel.com, pbonzini@...hat.com,
sandipan.das@....com, seanjc@...gle.com, tglx@...utronix.de, x86@...nel.org,
Jim Mattson <jmattson@...gle.com>, Venkatesh Srinivas <venkateshs@...omium.org>,
Tom Lendacky <thomas.lendacky@....com>
Subject: [PATCH v5 2/4] x86/cpufeatures: Define X86_FEATURE_AMD_IBPB_RET
AMD's initial implementation of IBPB did not clear the return address
predictor. Beginning with Zen4, AMD's IBPB *does* clear the return
address predictor. This behavior is enumerated by
CPUID.80000008H:EBX.IBPB_RET[bit 30].
Define X86_FEATURE_AMD_IBPB_RET for use in KVM_GET_SUPPORTED_CPUID,
when determining cross-vendor capabilities.
Suggested-by: Venkatesh Srinivas <venkateshs@...omium.org>
Signed-off-by: Jim Mattson <jmattson@...gle.com>
Reviewed-by: Tom Lendacky <thomas.lendacky@....com>
Reviewed-by: Thomas Gleixner <tglx@...utronix.de>
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 644b3e1e1ab6..a222a24677d7 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -348,6 +348,7 @@
#define X86_FEATURE_CPPC (13*32+27) /* "cppc" Collaborative Processor Performance Control */
#define X86_FEATURE_AMD_PSFD (13*32+28) /* Predictive Store Forwarding Disable */
#define X86_FEATURE_BTC_NO (13*32+29) /* Not vulnerable to Branch Type Confusion */
+#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* IBPB clears return address predictor */
#define X86_FEATURE_BRS (13*32+31) /* "brs" Branch Sampling available */
/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
--
2.47.0.rc1.288.g06298d1525-goog
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