linux-kernel - RE: [PATCH v2] arm64: dts: renesas: r9a09g057: Add OPP table

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID:
 <TY3PR01MB1134648DE5396A9ED9227BEB186792@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Fri, 11 Oct 2024 07:43:26 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
CC: "Lad, Prabhakar" <prabhakar.csengg@...il.com>, Magnus Damm
	<magnus.damm@...il.com>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
	<krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, Prabhakar Mahadev Lad
	<prabhakar.mahadev-lad.rj@...renesas.com>
Subject: RE: [PATCH v2] arm64: dts: renesas: r9a09g057: Add OPP table

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@...ux-m68k.org>
> Sent: Wednesday, October 9, 2024 11:09 AM
> Subject: Re: [PATCH v2] arm64: dts: renesas: r9a09g057: Add OPP table
> 
> Hi Biju,
> 
> On Wed, Oct 9, 2024 at 11:41 AM Biju Das <biju.das.jz@...renesas.com> wrote:
> > > From: Geert Uytterhoeven <geert@...ux-m68k.org> On Tue, Oct 8, 2024
> > > at 10:10 PM Lad, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > > > On Tue, Oct 8, 2024 at 6:33 PM Biju Das <biju.das.jz@...renesas.com> wrote:
> > > > > > From: Biju Das <biju.das.jz@...renesas.com>
> > > > > > > From: Prabhakar <prabhakar.csengg@...il.com>
> > > > > > > From: Lad Prabhakar
> > > > > > > <prabhakar.mahadev-lad.rj@...renesas.com>
> > > > > > >
> > > > > > > Add OPP table for RZ/V2H(P) SoC.
> > > > > > >
> > > > > > > Signed-off-by: Lad Prabhakar
> > > > > > > <prabhakar.mahadev-lad.rj@...renesas.com>
> > > > > > > ---
> > > > > > > v1->v2
> > > > > > > - Set opp-microvolt to 800000 for frequencies below 1.1GHz
> > > > > > > ---
> > > > > > >  arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41
> > > > > > > ++++++++++++++++++++++
> > > > > > >  1 file changed, 41 insertions(+)
> > > > > > >
> > > > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > > > > b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > > > > index 1ad5a1b6917f..4bbe75b81f54 100644
> > > > > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > > > > @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk {
> > > > > > >             clock-frequency = <0>;
> > > > > > >     };
> > > > > > >
> > > > > > > +   /*
> > > > > > > +    * The default cluster table is based on the assumption that the PLLCA55 clock
> > > > > > > +    * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
> > > > > > > +    * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
> > > > > > > +    * clocked to 1.8GHz as well). The table below should be overridden in the board
> > > > > > > +    * DTS based on the PLLCA55 clock frequency.
> > > > > > > +    */
> > > > > > > +   cluster0_opp: opp-table-0 {
> > > > > > > +           compatible = "operating-points-v2";
> > > > > > > +
> > > > > > > +           opp-1700000000 {
> > > > > > > +                   opp-hz = /bits/ 64 <1700000000>;
> > > > > > > +                   opp-microvolt = <900000>;
> > > > > >
> > > > > > Not sure CA-55 can change voltage from 800mV to 900mV??
> > > > > > Based on Power Domain Control, it needs to be in AWO mode for changing the PD_CA55 voltage.
> > > > > >
> > > > > > The manual says OD voltage is 0.9V and ND voltage is 0.8V.
> > > > > >
> > > > > > Is 1.7GHZ is ND or OD?
> > > > >
> > > > > {1.7,1.6,1.5 GHz} is enabled when VDD09_CA55 is at 0.9 V and for
> > > > > 1.1 GHz it is 0.8V.
> > > > >
> > > > > Maybe when you do /2, /4, /8 using dividers, the voltage may be
> > > > > still the same??
> > > > >
> > > > I think you are right when BOOTPLLCA[1:0] pins are set to 1.7GHz
> > > > the
> > > > VDD09_CA55 is at 0.9 V, further dividing the clock shouldnt affect
> > > > the voltage levels at the PMIC output.
> > > >
> > > > Geert, please let me know if my understanding is incorrect.
> > >
> > > The actual VDD09_CA55 voltage is controlled by the external PMIC
> > > (RAA215300).  It is the responsibility of the system designer to
> > > make sure VDD09_CA55 is at 0.9V when BOOTPLLCA[1:0] is strapped for OD, as CPU core clock rates
> higher than 1.1 GHz need a higher core voltage.
> > > I don't think it hurts to supply the higher core voltage while
> > > running the CPU core at low core frequencies, except for extra power consumption.
> > >
> > > To control VDD09_CA55 dynamically, the CPU cores should have
> > > cpu-supply properties pointing to the regulator controlling it (raa215300).
> >
> > This needs a big work(see: 4.5.3.1.3 PD_CA55 area voltage change).
> > CA-55 needs to signal CM-33 so that it switches to AWO mode(Only CM-33
> > is active) and In AWO mode, CM33 is in charge of changing CA55 voltage
> > and then switches to ALL-ON mode
> >
> 
> Ugh, this is indeed much more complicated than on other SoCs.
> So basically you are stuck with the initial voltage settings.

FYI, I got confirmation that 1.7GHz,0.9V is Normal drive and
It is the default for RZ/V2H and upcoming RZ/G3E SoCs.

Cheers,
Biju