linux-kernel - RE: [PATCH v2 6/7] iio: adc: ad485x: add ad485x driver

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Message-ID:
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Date: Fri, 11 Oct 2024 11:27:15 +0000
From: "Miclaus, Antoniu" <Antoniu.Miclaus@...log.com>
To: David Lechner <dlechner@...libre.com>,
        Andy Shevchenko
	<andy.shevchenko@...il.com>
CC: Jonathan Cameron <jic23@...nel.org>, Lars-Peter Clausen <lars@...afoo.de>,
        "Hennerich, Michael" <Michael.Hennerich@...log.com>,
        Rob Herring
	<robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
	<conor+dt@...nel.org>, "Sa, Nuno" <Nuno.Sa@...log.com>,
        Olivier Moysan
	<olivier.moysan@...s.st.com>,
        Uwe Kleine-König
	<ukleinek@...nel.org>,
        Andy Shevchenko <andy@...nel.org>,
        "Schmitt, Marcelo"
	<Marcelo.Schmitt@...log.com>,
        Mike Looijmans <mike.looijmans@...ic.nl>,
        Marius Cristea <marius.cristea@...rochip.com>,
        Dumitru Ceclan
	<mitrutzceclan@...il.com>,
        AngeloGioacchino Del Regno
	<angelogioacchino.delregno@...labora.com>,
        Alisa-Dariana Roman
	<alisadariana@...il.com>,
        Ivan Mikhaylov <fr0st61te@...il.com>,
        "Cuciurean,
 Sergiu" <Sergiu.Cuciurean@...log.com>,
        "Bogdan, Dragos"
	<Dragos.Bogdan@...log.com>,
        "linux-iio@...r.kernel.org"
	<linux-iio@...r.kernel.org>,
        "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>,
        "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>,
        "linux-pwm@...r.kernel.org"
	<linux-pwm@...r.kernel.org>
Subject: RE: [PATCH v2 6/7] iio: adc: ad485x: add ad485x driver

> On 10/8/24 5:48 AM, Miclaus, Antoniu wrote:
> >>> +static int ad485x_get_calibscale(struct ad485x_state *st, int ch, int *val,
> int
> >> *val2)
> >>> +{
> >>> +       unsigned int reg_val;
> >>> +       int gain;
> >>
> >> Should be u8 gain[2] and...
> >
> > As discussed in previous patch series, the bulk operations won't work for
> these
> > chips. The CS needs to be raised between each byte read/written.
> >
> 
> So the datasheet is wrong and Streaming Instruction Mode doesn't actually
> work?
> 
> There is also Nonstreaming Instruction Mode if we need to read/write
> nonconsecutive
> registers without deasserting CS.

The chip was set to Nonstreaming Instruction Mode from the start in the ad485x_setup() function.

And the datasheet specifies (page 49 of 70):
"In nonstreaming instruction mode, one or more SPI transactions can be provided in
a single SPI frame."

So I guess it is an error in the datasheet.