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Message-ID: <20241011120520.140318-5-y.oudjana@protonmail.com>
Date: Fri, 11 Oct 2024 15:03:49 +0300
From: Yassine Oudjana <yassine.oudjana@...il.com>
To: Sean Wang <sean.wang@...nel.org>,
Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Cc: Yassine Oudjana <y.oudjana@...tonmail.com>,
Yassine Oudjana <yassine.oudjana@...il.com>,
Andy Teng <andy.teng@...iatek.com>,
linux-mediatek@...ts.infradead.org,
linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Subject: [PATCH v6 4/8] arm64: dts: mediatek: mt6797: Make pin configuration nodes follow DT bindings
From: Yassine Oudjana <y.oudjana@...tonmail.com>
Add -pins suffix to pin configuration nodes to follow DT bindings
and pass dtbs_check.
Signed-off-by: Yassine Oudjana <y.oudjana@...tonmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
---
arch/arm64/boot/dts/mediatek/mt6797.dtsi | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
index 0e9d11b4585be..a786d1d08f683 100644
--- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
@@ -135,70 +135,70 @@ pio: pinctrl@...05000 {
gpio-controller;
#gpio-cells = <2>;
- uart0_pins_a: uart0 {
+ uart0_pins_a: uart0-pins {
pins0 {
pinmux = <MT6797_GPIO234__FUNC_UTXD0>,
<MT6797_GPIO235__FUNC_URXD0>;
};
};
- uart1_pins_a: uart1 {
+ uart1_pins_a: uart1-pins {
pins1 {
pinmux = <MT6797_GPIO232__FUNC_URXD1>,
<MT6797_GPIO233__FUNC_UTXD1>;
};
};
- i2c0_pins_a: i2c0 {
+ i2c0_pins_a: i2c0-pins {
pins0 {
pinmux = <MT6797_GPIO37__FUNC_SCL0_0>,
<MT6797_GPIO38__FUNC_SDA0_0>;
};
};
- i2c1_pins_a: i2c1 {
+ i2c1_pins_a: i2c1-pins {
pins1 {
pinmux = <MT6797_GPIO55__FUNC_SCL1_0>,
<MT6797_GPIO56__FUNC_SDA1_0>;
};
};
- i2c2_pins_a: i2c2 {
+ i2c2_pins_a: i2c2-pins {
pins2 {
pinmux = <MT6797_GPIO96__FUNC_SCL2_0>,
<MT6797_GPIO95__FUNC_SDA2_0>;
};
};
- i2c3_pins_a: i2c3 {
+ i2c3_pins_a: i2c3-pins {
pins3 {
pinmux = <MT6797_GPIO75__FUNC_SDA3_0>,
<MT6797_GPIO74__FUNC_SCL3_0>;
};
};
- i2c4_pins_a: i2c4 {
+ i2c4_pins_a: i2c4-pins {
pins4 {
pinmux = <MT6797_GPIO238__FUNC_SDA4_0>,
<MT6797_GPIO239__FUNC_SCL4_0>;
};
};
- i2c5_pins_a: i2c5 {
+ i2c5_pins_a: i2c5-pins {
pins5 {
pinmux = <MT6797_GPIO240__FUNC_SDA5_0>,
<MT6797_GPIO241__FUNC_SCL5_0>;
};
};
- i2c6_pins_a: i2c6 {
+ i2c6_pins_a: i2c6-pins {
pins6 {
pinmux = <MT6797_GPIO152__FUNC_SDA6_0>,
<MT6797_GPIO151__FUNC_SCL6_0>;
};
};
- i2c7_pins_a: i2c7 {
+ i2c7_pins_a: i2c7-pins {
pins7 {
pinmux = <MT6797_GPIO154__FUNC_SDA7_0>,
<MT6797_GPIO153__FUNC_SCL7_0>;
--
2.46.2
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