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Message-ID: <CAMRc=MftQBH_d4Ew_5jdqqk1WpM511huWJH2ZDwnhXVYDboYLg@mail.gmail.com>
Date: Mon, 14 Oct 2024 15:05:55 +0200
From: Bartosz Golaszewski <brgl@...ev.pl>
To: Kuldeep Singh <quic_kuldsing@...cinc.com>
Cc: Bjorn Andersson <andersson@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>, 
	Bartosz Golaszewski <bartosz.golaszewski@...aro.org>, linux-arm-msm@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Qingqing Zhou <quic_qqzhou@...cinc.com>
Subject: Re: [PATCH v2 1/2] firmware: qcom: scm: Return -EOPNOTSUPP for
 unsupported SHM bridge enabling

On Mon, Oct 14, 2024 at 1:19 PM Kuldeep Singh <quic_kuldsing@...cinc.com> wrote:
>
> From: Qingqing Zhou <quic_qqzhou@...cinc.com>
>
> When enabling SHM bridge, QTEE returns 0 and sets error 4 in result to
> qcom_scm for unsupported platforms. Currently, tzmem interprets this as
> an unknown error rather than recognizing it as an unsupported platform.
>
> Error log:
> [    0.177224] qcom_scm firmware:scm: error (____ptrval____): Failed to enable the TrustZone memory allocator
> [    0.177244] qcom_scm firmware:scm: probe with driver qcom_scm failed with error 4
>
> To address this, modify the function call qcom_scm_shm_bridge_enable()
> to remap result to indicate an unsupported error. This way, tzmem will
> correctly identify it as an unsupported platform case instead of
> reporting it as an error.
>
> Fixes: 178e19c0df1b ("firmware: qcom: scm: add support for SHM bridge operations")
> Signed-off-by: Qingqing Zhou <quic_qqzhou@...cinc.com>
> Co-developed-by: Kuldeep Singh <quic_kuldsing@...cinc.com>
> Signed-off-by: Kuldeep Singh <quic_kuldsing@...cinc.com>
> ---
>  drivers/firmware/qcom/qcom_scm.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c
> index 10986cb11ec0..0df81a9ed438 100644
> --- a/drivers/firmware/qcom/qcom_scm.c
> +++ b/drivers/firmware/qcom/qcom_scm.c
> @@ -112,6 +112,7 @@ enum qcom_scm_qseecom_tz_cmd_info {
>  };
>
>  #define QSEECOM_MAX_APP_NAME_SIZE              64
> +#define SHMBRIDGE_RESULT_NOTSUPP               4
>
>  /* Each bit configures cold/warm boot address for one of the 4 CPUs */
>  static const u8 qcom_scm_cpu_cold_bits[QCOM_SCM_BOOT_MAX_CPUS] = {
> @@ -1361,6 +1362,8 @@ EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh_available);
>
>  int qcom_scm_shm_bridge_enable(void)
>  {
> +       int ret;
> +
>         struct qcom_scm_desc desc = {
>                 .svc = QCOM_SCM_SVC_MP,
>                 .cmd = QCOM_SCM_MP_SHM_BRIDGE_ENABLE,
> @@ -1373,7 +1376,15 @@ int qcom_scm_shm_bridge_enable(void)
>                                           QCOM_SCM_MP_SHM_BRIDGE_ENABLE))
>                 return -EOPNOTSUPP;
>
> -       return qcom_scm_call(__scm->dev, &desc, &res) ?: res.result[0];
> +       ret = qcom_scm_call(__scm->dev, &desc, &res);
> +
> +       if (ret)
> +               return ret;
> +
> +       if (res.result[0] == SHMBRIDGE_RESULT_NOTSUPP)
> +               return -EOPNOTSUPP;
> +
> +       return res.result[0];
>  }
>  EXPORT_SYMBOL_GPL(qcom_scm_shm_bridge_enable);
>
> --
> 2.34.1
>
>

The patch looks correct to me and like something that should go upstream.

Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>

That being said, this doesn't seem to address any of the issues that
we saw with SHM Bridge and it still leads to a crash on sc8180x. :(

Bart

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