linux-kernel - Re: [PATCH v6 6/8] PCI: qcom: Fix the ops for SC8280X family SoC

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Message-ID: <20241014171807.GA612411@bhelgaas>
Date: Mon, 14 Oct 2024 12:18:07 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: Qiang Yu <quic_qianyu@...cinc.com>
Cc: manivannan.sadhasivam@...aro.org, vkoul@...nel.org, kishon@...nel.org,
	robh@...nel.org, andersson@...nel.org, konradybcio@...nel.org,
	krzk+dt@...nel.org, conor+dt@...nel.org, mturquette@...libre.com,
	sboyd@...nel.org, abel.vesa@...aro.org, quic_msarkar@...cinc.com,
	quic_devipriy@...cinc.com, dmitry.baryshkov@...aro.org,
	kw@...ux.com, lpieralisi@...nel.org, neil.armstrong@...aro.org,
	linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
	linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
	devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
	Johan Hovold <johan+linaro@...nel.org>
Subject: Re: [PATCH v6 6/8] PCI: qcom: Fix the ops for SC8280X family SoC

[+cc Johan; if you tag a commit with Fixes:, please cc the author of
that commit!]

On Fri, Oct 11, 2024 at 03:41:40AM -0700, Qiang Yu wrote:
> On SC8280X family SoC, PCIe controllers are connected to SMMUv3, hence
> they don't need the config_sid() callback in ops_1_9_0 struct. Fix it by
> introducing a new ops struct, namely ops_1_21_0, so that BDF2SID mapping
> won't be configured during init.

Can you make the subject line say something specific about what this
patch does?  "Fix the ops" really doesn't include any useful
information.

Based on the Fixes: below, this has to do with ASPM, so the subject
line (and the commit log) should probably say something about ASPM.

I don't see the connection between your mention of SMMUv3 and ASPM.
Are there two logical changes here that should be two separate
patches?

> Fixes: d1997c987814 ("PCI: qcom: Disable ASPM L0s for sc8280xp, sa8540p and sa8295p")
> Signed-off-by: Qiang Yu <quic_qianyu@...cinc.com>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 88a98be930e3..468bd4242e61 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1367,6 +1367,16 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
>  	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>  };
>  
> +/* Qcom IP rev.: 1.21.0 */
> +static const struct qcom_pcie_ops ops_1_21_0 = {
> +	.get_resources = qcom_pcie_get_resources_2_7_0,
> +	.init = qcom_pcie_init_2_7_0,
> +	.post_init = qcom_pcie_post_init_2_7_0,
> +	.host_post_init = qcom_pcie_host_post_init_2_7_0,
> +	.deinit = qcom_pcie_deinit_2_7_0,
> +	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
> +};
> +
>  static const struct qcom_pcie_cfg cfg_1_0_0 = {
>  	.ops = &ops_1_0_0,
>  };
> @@ -1405,7 +1415,7 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
>  };
>  
>  static const struct qcom_pcie_cfg cfg_sc8280xp = {
> -	.ops = &ops_1_9_0,
> +	.ops = &ops_1_21_0,
>  	.no_l0s = true,
>  };
>  
> -- 
> 2.34.1
>