lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20241014172930.GA612951@bhelgaas>
Date: Mon, 14 Oct 2024 12:29:30 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: Terry Bowman <Terry.Bowman@....com>
Cc: ming4.li@...el.com, linux-cxl@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
	dave@...olabs.net, jonathan.cameron@...wei.com,
	dave.jiang@...el.com, alison.schofield@...el.com,
	vishal.l.verma@...el.com, dan.j.williams@...el.com,
	bhelgaas@...gle.com, mahesh@...ux.ibm.com, oohall@...il.com,
	Benjamin.Cheatham@....com, rrichter@....com,
	nathan.fontenot@....com, smita.koralahallichannabasappa@....com
Subject: Re: [PATCH 0/15] Enable CXL PCIe port protocol error handling and
 logging

On Mon, Oct 14, 2024 at 12:22:08PM -0500, Terry Bowman wrote:
> On 10/10/24 14:07, Bjorn Helgaas wrote:
> > On Tue, Oct 08, 2024 at 05:16:42PM -0500, Terry Bowman wrote:
> >> This is a continuation of the CXL port error handling RFC from earlier.[1]
> >> The RFC resulted in the decision to add CXL PCIe port error handling to
> >> the existing RCH downstream port handling. This patchset adds the CXL PCIe
> >> port handling and logging.
> ...

> >>     Downstream switch port CE:
> >>     root@...wman-cxl:~/aer-inject# ./ds-ce-inject.sh
> >>     [  177.114442] pcieport 0000:0c:00.0: aer_inject: Injecting errors 00004000/00000000 into device 0000:0e:00.0
> >>     [  177.115602] pcieport 0000:0c:00.0: AER: Correctable error message received from 0000:0e:00.0
> >>     [  177.116973] pcieport 0000:0e:00.0: PCIe Bus Error: severity=Correctable, type=Transaction Layer, (Receiver ID)
> >>     [  177.117985] pcieport 0000:0e:00.0:   device [19e5:a129] error status/mask=00004000/0000a000
> >>     [  177.118809] pcieport 0000:0e:00.0:    [14] CorrIntErr
> >>     [  177.119521] aer_event: 0000:0e:00.0 PCIe Bus Error: severity=Corrected, Corrected Internal Error, TLP Header=Not available
> >>     [  177.119521]
> >>     [  177.122037] cxl_port_aer_correctable_error: device=0000:0e:00.0 host=0000:0d:00.0 status='Received Error From Physical Layer'
> > 
> > Thanks for the hints about how to test this; it's helpful to have
> > those in the email archives.  Remove the timestamps and non-relevant
> > call trace entries unless they add useful information.  AFAICT they're
> > just distractions in this case.
> 
> I'll remove the test logging and details from the cover sheet. I'm
> unable to find how to attach using git tools. Instead of an
> atatachment, I can locate the log files and details on a public
> github. Let me know if this is not acceptable.

It's fine to keep this in the cover sheet, and I'd rather have it
there, where lore will archive it reliably forever, than to have a
pointer to some other github that may eventually disappear even though
it's public today.

I just meant to remove irrelevant information like the timestamps.

Bjorn

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ