linux-kernel - [PATCH RFC 1/2] dt-bindings: iommu: arm,smmu-v3: introduce nxp,imx95-bypass-sid-zero

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Message-Id: <20241015-smmuv3-v1-1-e4b9ed1b5501@nxp.com>
Date: Tue, 15 Oct 2024 11:14:42 +0800
From: "Peng Fan (OSS)" <peng.fan@....nxp.com>
To: Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>, 
 Joerg Roedel <joro@...tes.org>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>
Cc: Joy Zou <joy.zou@....com>, linux-arm-kernel@...ts.infradead.org, 
 iommu@...ts.linux.dev, devicetree@...r.kernel.org, 
 linux-kernel@...r.kernel.org, Peng Fan <peng.fan@....com>, 
 Jason Gunthorpe <jgg@...pe.ca>
Subject: [PATCH RFC 1/2] dt-bindings: iommu: arm,smmu-v3: introduce
 nxp,imx95-bypass-sid-zero

From: Peng Fan <peng.fan@....com>

i.MX95 eDMA3 connects to DSU ACP, supporting dma coherent memory to
memory operations. However TBU is in the path between eDMA3 and ACP,
need to bypass the default SID 0 to make eDMA3 work properly.

Introduce the property "nxp,imx95-bypass-sid-zero" for bypassing SID 0.

Signed-off-by: Peng Fan <peng.fan@....com>
---
 Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
index 75fcf4cb52d9f6449238578f20288966af35cab3..88ab908154e31aabf98f3bbe4df348956f49d5e1 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
@@ -69,6 +69,10 @@ properties:
       register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
       doesn't support SMMU page1 register space.
 
+  nxp,imx95-bypass-sid-zero:
+    type: boolean
+    description: StreamID 0 that needs transaction set as bypass mode.
+
 required:
   - compatible
   - reg

-- 
2.37.1