linux-kernel - Re: [PATCH 3/7] x86/resctrl: Introduce sdciae_capable in rdt

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Message-ID: <bf67bc4e-9cf8-4cac-9ffb-2d4f81ab7e30@amd.com>
Date: Tue, 15 Oct 2024 15:40:30 -0500
From: "Moger, Babu" <babu.moger@....com>
To: Reinette Chatre <reinette.chatre@...el.com>, corbet@....net,
 tglx@...utronix.de, mingo@...hat.com, bp@...en8.de,
 dave.hansen@...ux.intel.com, x86@...nel.org
Cc: fenghua.yu@...el.com, hpa@...or.com, paulmck@...nel.org,
 thuth@...hat.com, xiongwei.song@...driver.com, ardb@...nel.org,
 pawan.kumar.gupta@...ux.intel.com, daniel.sneddon@...ux.intel.com,
 sandipan.das@....com, kai.huang@...el.com, peterz@...radead.org,
 kan.liang@...ux.intel.com, pbonzini@...hat.com, xin3.li@...el.com,
 ebiggers@...gle.com, alexandre.chartre@...cle.com, perry.yuan@....com,
 tan.shaopeng@...itsu.com, james.morse@....com, tony.luck@...el.com,
 maciej.wieczor-retman@...el.com, linux-doc@...r.kernel.org,
 linux-kernel@...r.kernel.org, peternewman@...gle.com, eranian@...gle.com
Subject: Re: [PATCH 3/7] x86/resctrl: Introduce sdciae_capable in rdt_resource

Hi Reinette,

On 9/19/24 10:33, Reinette Chatre wrote:
> Hi Babu,
> 
> On 9/18/24 11:22 AM, Moger, Babu wrote:
>>
>>
>> On 9/18/24 10:27, Moger, Babu wrote:
>>> Hi Reinette,
>>>
>>> On 9/13/24 15:45, Reinette Chatre wrote:
>>>> Hi Babu,
>>>>
>>>> On 8/16/24 9:16 AM, Babu Moger wrote:
>>>>> Detect SDCIAE`(L3 Smart Data Cache Injection Allocation Enforcement)
>>>>
>>>> (stray ` char)
>>>
>>> Sure.
>>>
>>>>
>>>>> feature and initialize sdciae_capable.
>>>>
>>>> (This is a repeat of the discussion we had surrounding the ABMC feature.)
>>>>
>>>> By adding "sdciae_capable" to struct rdt_resource the "sdciae" feature
>>>> becomes a resctrl fs feature. Any other architecture that has a "similar
>>>> but perhaps not identical feature to AMD's SDCIAE" will be forced to also
>>>> call it "sdciae" ... sdciae seems like a marketing name to me and resctrl
>>>> needs something generic that could later be built on (if needed) by other
>>>> architectures.
>>>
>>> How about "cache_inject_capable" ?
>>>
>>> This seems generic. I will change the description also.
>>>
>>
>> Basically, this feature reserves specific CLOS for SDCI cache.
>>
>> We can also name "clos_reserve_capable".
> 
> Naming is always complicated. I think we should try to stay away from
> "clos" in a generic name since that creates problem when trying to
> apply it to Arm and is very specific to how AMD implements this
> feature. "cache_inject_capable" does sound much better to me ...
> it also looks like this may be more appropriate as a property
> of struct resctrl_cache?

Coming back to this again, I feel 'cache_inject_capable' is kind of very
generic. Cache injection term is used very generically everywhere.

Does  'cache_reserve_capable" sound good ?  This is inside the resctrl
subsystem. We know what it is referring to.

-- 
Thanks
Babu Moger