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Message-ID: <2edf63cd-66e2-4050-80dd-800ed77ef5e1@kernel.org>
Date: Tue, 15 Oct 2024 09:02:19 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Igor Belwon <igor.belwon@...tallysanemainliners.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Alim Akhtar <alim.akhtar@...sung.com>,
Sylwester Nawrocki <s.nawrocki@...sung.com>,
Linus Walleij <linus.walleij@...aro.org>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org,
linux-gpio@...r.kernel.org, david@...nlining.org
Subject: Re: [PATCH v1 6/7] arm64: dts: exynos: Add initial support for the
Exynos 990 SoC
On 15/10/2024 08:27, Igor Belwon wrote:
> The Exynos 990 SoC is an ARMv8 mobile SoC found in Samsung Galaxy N/S20
> series phones (x1sxxx, c1sxxx). Add minimal support for this SoC,
> including:
>
...
> + /* There's no PMU model for cluster2, which are the Mongoose cores. */
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> +
> + core1 {
> + cpu = <&cpu1>;
> + };
> +
> + core2 {
> + cpu = <&cpu2>;
> + };
> +
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu4>;
> + };
> +
> + core1 {
> + cpu = <&cpu5>;
> + };
> + };
> +
> + cluster2 {
> + core0 {
> + cpu = <&cpu6>;
> + };
> +
> + core1 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x0>;
> + enable-method = "psci";
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x1>;
> + enable-method = "psci";
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x2>;
> + enable-method = "psci";
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x3>;
> + enable-method = "psci";
> + };
> +
> + cpu4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a76";
> + reg = <0x4>;
> + enable-method = "psci";
> + };
> +
> + cpu5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a76";
> + reg = <0x5>;
> + enable-method = "psci";
> + };
> +
> + cpu6: cpu@200 {
> + device_type = "cpu";
> + compatible = "samsung,mongoose-m5";
> + reg = <0x6>;
> + enable-method = "psci";
> + };
> +
> + cpu7: cpu@201 {
> + device_type = "cpu";
> + compatible = "samsung,mongoose-m5";
> + reg = <0x7>;
> + enable-method = "psci";
> + };
> +
Stray blank line
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "hvc";
> + };
> +
> + oscclk: osc-clock {
clock-osc and keep order by node name
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-output-names = "oscclk";
> + };
> +
> + soc: soc@0 {
> + compatible = "simple-bus";
> + ranges = <0x0 0x0 0x0 0x20000000>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + chipid@...00000 {
> + compatible = "samsung,exynos990-chipid",
> + "samsung,exynos850-chipid";
> + reg = <0x10000000 0x100>;
> + };
> +
> + gic: interrupt-controller@...01000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x10101000 0x1000>,
> + <0x10102000 0x1000>,
> + <0x10104000 0x2000>,
> + <0x10106000 0x2000>;
reg is the second property
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
> + IRQ_TYPE_LEVEL_HIGH)>;
> + #address-cells = <0>;
> + #size-cells = <1>;
> + };
> +
> + pinctrl_cmgp: pinctrl@...30000 {
Keep order by unit address.
> + compatible = "samsung,exynos990-pinctrl";
> + reg = <0x15c30000 0x1000>;
> + };
> +
> + pinctrl_hsi1: pinctrl@...40000 {
> + compatible = "samsung,exynos990-pinctrl";
> + reg = <0x13040000 0x1000>;
> + interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pinctrl_hsi2: pinctrl@...30000 {
> + compatible = "samsung,exynos990-pinctrl";
> + reg = <0x13c30000 0x1000>;
> + interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pinctrl_peric0: pinctrl@...30000 {
> + compatible = "samsung,exynos990-pinctrl";
> + reg = <0x10430000 0x1000>;
> + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pinctrl_peric1: pinctrl@...30000 {
> + compatible = "samsung,exynos990-pinctrl";
> + reg = <0x10730000 0x1000>;
> + interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pinctrl_vts: pinctrl@...80000 {
> + compatible = "samsung,exynos990-pinctrl";
> + reg = <0x15580000 0x1000>;
> + };
> +
> + pinctrl_alive: pinctrl@...50000 {
> + compatible = "samsung,exynos990-pinctrl";
> + reg = <0x15850000 0x1000>;
> +
> + wakeup-interrupt-controller {
> + compatible = "samsung,exynos990-wakeup-eint",
> + "samsung,exynos7-wakeup-eint";
> + };
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> +
> + /*
> + * Non-updatable, broken stock Samsung bootloader does not
> + * configure CNTFRQ_EL0
> + */
> + clock-frequency = <26000000>;
> + };
> +};
> +
> +#include "exynos990-pinctrl.dtsi"
Best regards,
Krzysztof
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