lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <ca29046a-29db-4bb0-815a-c482385194c7@intel.com>
Date: Wed, 16 Oct 2024 08:54:18 -0700
From: Reinette Chatre <reinette.chatre@...el.com>
To: <babu.moger@....com>, <corbet@....net>, <tglx@...utronix.de>,
	<mingo@...hat.com>, <bp@...en8.de>, <dave.hansen@...ux.intel.com>,
	<x86@...nel.org>
CC: <fenghua.yu@...el.com>, <hpa@...or.com>, <paulmck@...nel.org>,
	<thuth@...hat.com>, <xiongwei.song@...driver.com>, <ardb@...nel.org>,
	<pawan.kumar.gupta@...ux.intel.com>, <daniel.sneddon@...ux.intel.com>,
	<sandipan.das@....com>, <kai.huang@...el.com>, <peterz@...radead.org>,
	<kan.liang@...ux.intel.com>, <pbonzini@...hat.com>, <xin3.li@...el.com>,
	<ebiggers@...gle.com>, <alexandre.chartre@...cle.com>, <perry.yuan@....com>,
	<tan.shaopeng@...itsu.com>, <james.morse@....com>, <tony.luck@...el.com>,
	<maciej.wieczor-retman@...el.com>, <linux-doc@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, <peternewman@...gle.com>,
	<eranian@...gle.com>
Subject: Re: [PATCH 3/7] x86/resctrl: Introduce sdciae_capable in rdt_resource

Hi Babu,

On 10/15/24 1:40 PM, Moger, Babu wrote:
> On 9/19/24 10:33, Reinette Chatre wrote:
>> On 9/18/24 11:22 AM, Moger, Babu wrote:
>>> On 9/18/24 10:27, Moger, Babu wrote:
>>>> On 9/13/24 15:45, Reinette Chatre wrote:
>>>>> On 8/16/24 9:16 AM, Babu Moger wrote:
>>>>>> Detect SDCIAE`(L3 Smart Data Cache Injection Allocation Enforcement)
>>>>>
>>>>> (stray ` char)
>>>>
>>>> Sure.
>>>>
>>>>>
>>>>>> feature and initialize sdciae_capable.
>>>>>
>>>>> (This is a repeat of the discussion we had surrounding the ABMC feature.)
>>>>>
>>>>> By adding "sdciae_capable" to struct rdt_resource the "sdciae" feature
>>>>> becomes a resctrl fs feature. Any other architecture that has a "similar
>>>>> but perhaps not identical feature to AMD's SDCIAE" will be forced to also
>>>>> call it "sdciae" ... sdciae seems like a marketing name to me and resctrl
>>>>> needs something generic that could later be built on (if needed) by other
>>>>> architectures.
>>>>
>>>> How about "cache_inject_capable" ?
>>>>
>>>> This seems generic. I will change the description also.
>>>>
>>>
>>> Basically, this feature reserves specific CLOS for SDCI cache.
>>>
>>> We can also name "clos_reserve_capable".
>>
>> Naming is always complicated. I think we should try to stay away from
>> "clos" in a generic name since that creates problem when trying to
>> apply it to Arm and is very specific to how AMD implements this
>> feature. "cache_inject_capable" does sound much better to me ...
>> it also looks like this may be more appropriate as a property
>> of struct resctrl_cache?
> 
> Coming back to this again, I feel 'cache_inject_capable' is kind of very
> generic. Cache injection term is used very generically everywhere.
> 
> Does  'cache_reserve_capable" sound good ?  This is inside the resctrl
> subsystem. We know what it is referring to.
> 

Since this is inside resctrl "cache_reserve_capable" sounds like existing
CAT to me. Could it help if the term "io" appears in the name? Something like
"io_reserve_capable"? When this is a member of struct resctrl_cache it should
be implicit that it refers to the cache.

Reinette

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ