linux-kernel - Re: [PATCH 15/15] cxl/pci: Enable internal CE/UCE interrupts for CXL PCIe port devices

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Message-ID: <20241016182110.00003455@Huawei.com>
Date: Wed, 16 Oct 2024 18:21:10 +0100
From: Jonathan Cameron <Jonathan.Cameron@...wei.com>
To: Terry Bowman <terry.bowman@....com>
CC: <ming4.li@...el.com>, <linux-cxl@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, <linux-pci@...r.kernel.org>,
	<dave@...olabs.net>, <dave.jiang@...el.com>, <alison.schofield@...el.com>,
	<vishal.l.verma@...el.com>, <dan.j.williams@...el.com>,
	<bhelgaas@...gle.com>, <mahesh@...ux.ibm.com>, <oohall@...il.com>,
	<Benjamin.Cheatham@....com>, <rrichter@....com>, <nathan.fontenot@....com>,
	<smita.koralahallichannabasappa@....com>
Subject: Re: [PATCH 15/15] cxl/pci: Enable internal CE/UCE interrupts for
 CXL PCIe port devices

On Tue, 8 Oct 2024 17:16:57 -0500
Terry Bowman <terry.bowman@....com> wrote:

> The AER service drivers and CXL drivers are updated to handle PCIe
> port protocol errors. But, the PCIe AER correctable and uncorrectable
> internal errors are mask disabled for the PCIe port devices.
> 
> Enable the AER internal errors for CXL PCIe port devices.
> 
> Signed-off-by: Terry Bowman <terry.bowman@....com>

A while back I thought we had a discussion about just enabling these
for all devices and seeing if anyone screamed?

I'd love to do that rather than carefully enabling them for CXL devices
only ;)

If not, this looks fine to me.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>

> ---
>  drivers/cxl/core/pci.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 4706113d2582..1d84a7022c4d 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -908,6 +908,7 @@ EXPORT_SYMBOL_NS_GPL(cxl_port_err_detected, CXL);
>  
>  void cxl_uport_init_aer(struct cxl_port *port)
>  {
> +	struct pci_dev *pdev = to_pci_dev(port->uport_dev);
>  	/* uport may have more than 1 downstream EP. Check if already mapped. */
>  	if (port->uport_regs.ras) {
>  		dev_warn(&port->dev, "RAS is already mapped\n");
> @@ -920,12 +921,14 @@ void cxl_uport_init_aer(struct cxl_port *port)
>  		dev_err(&port->dev, "Failed to map RAS capability.\n");
>  		return;
>  	}
> +	pci_aer_unmask_internal_errors(pdev);
>  }
>  EXPORT_SYMBOL_NS_GPL(cxl_uport_init_aer, CXL);
>  
>  void cxl_dport_init_aer(struct cxl_dport *dport)
>  {
>  	struct device *dport_dev = dport->dport_dev;
> +	struct pci_dev *pdev = to_pci_dev(dport_dev);
>  
>  	if (dport->rch) {
>  		struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport_dev);
> @@ -949,6 +952,7 @@ void cxl_dport_init_aer(struct cxl_dport *dport)
>  		dev_err(dport_dev, "Failed to map RAS capability.\n");
>  		return;
>  	}
> +	pci_aer_unmask_internal_errors(pdev);
>  }
>  EXPORT_SYMBOL_NS_GPL(cxl_dport_init_aer, CXL);
>