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Message-ID: <20241016181207.qhjkhz266quak6ve@thinkpad>
Date: Wed, 16 Oct 2024 23:42:07 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: Frank Li <Frank.Li@....com>
Cc: Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kw@...ux.com>,
Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Abraham I <kishon@...nel.org>,
Saravana Kannan <saravanak@...gle.com>,
Jingoo Han <jingoohan1@...il.com>,
Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
Jesper Nilsson <jesper.nilsson@...s.com>,
Richard Zhu <hongxing.zhu@....com>,
Lucas Stach <l.stach@...gutronix.de>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...s.com, linux-arm-kernel@...ts.infradead.org,
imx@...ts.linux.dev,
Krzysztof Wilczyński <kwilczynski@...nel.org>
Subject: Re: [PATCH v2 3/4] PCI: imx6: Pass correct sub mode when calling
phy_set_mode_ext()
On Mon, Sep 23, 2024 at 02:59:21PM -0400, Frank Li wrote:
> Fix hardcoding to Root Complex (RC) mode by adding a drvdata mode check.
> Pass PHY_MODE_PCIE_EP if the PCI controller operates in Endpoint (EP) mode.
>
Patch descriptions should fit within 75 columns.
> Fixes: 8026f2d8e8a9 ("PCI: imx6: Call common PHY API to set mode, speed, and submode")
> Signed-off-by: Frank Li <Frank.Li@....com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
- Mani
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 808d1f1054173..bdc2b372e6c13 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -961,7 +961,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
> goto err_clk_disable;
> }
>
> - ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
> + ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE,
> + imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE ?
> + PHY_MODE_PCIE_EP : PHY_MODE_PCIE_RC);
> if (ret) {
> dev_err(dev, "unable to set PCIe PHY mode\n");
> goto err_phy_exit;
>
> --
> 2.34.1
>
--
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