linux-kernel - Re: [PATCH 1/4] clk: imx: lpcg-scu: SW workaround for errata (e10858)

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Message-ID: <98e82f4c4e6c62fe61d65ae03b027f79.sboyd@kernel.org>
Date: Wed, 16 Oct 2024 14:46:42 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Abel Vesa <abelvesa@...nel.org>, Aisheng Dong <aisheng.dong@....com>, Fabio Estevam <festevam@...il.com>, Michael Turquette <mturquette@...libre.com>, Peng Fan (OSS) <peng.fan@....nxp.com>, Pengutronix Kernel Team <kernel@...gutronix.de>, Sascha Hauer <s.hauer@...gutronix.de>, Shawn Guo <shawnguo@...nel.org>
Cc: linux-clk@...r.kernel.org, imx@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, Peng Fan <peng.fan@....com>
Subject: Re: [PATCH 1/4] clk: imx: lpcg-scu: SW workaround for errata (e10858)

Quoting Peng Fan (OSS) (2024-10-14 02:11:22)
> diff --git a/drivers/clk/imx/clk-lpcg-scu.c b/drivers/clk/imx/clk-lpcg-scu.c
> index dd5abd09f3e206a5073767561b517d5b3320b28c..2cffec0c42dccc256e8dc5e9181952e250870a76 100644
> --- a/drivers/clk/imx/clk-lpcg-scu.c
> +++ b/drivers/clk/imx/clk-lpcg-scu.c
> @@ -6,6 +6,7 @@
>  
>  #include <linux/bits.h>
>  #include <linux/clk-provider.h>
> +#include <linux/delay.h>
>  #include <linux/err.h>
>  #include <linux/io.h>
>  #include <linux/slab.h>
> @@ -41,6 +42,31 @@ struct clk_lpcg_scu {
>  
>  #define to_clk_lpcg_scu(_hw) container_of(_hw, struct clk_lpcg_scu, hw)
>  
> +/* e10858 -LPCG clock gating register synchronization errata */
> +static void lpcg_e10858_writel(ulong rate, void __iomem *reg, u32 val)

s/ulong/unsigned long/

> +{
> +       u32 reg1;
> +
> +       writel(val, reg);
> +
> +       if (rate >= 24000000 || rate == 0) {

Can be '24 * HZ_PER_MHZ'

> +               /*
> +                * The time taken to access the LPCG registers from the AP core
> +                * through the interconnect is longer than the minimum delay
> +                * of 4 clock cycles required by the errata.
> +                * Adding a readl will provide sufficient delay to prevent
> +                * back-to-back writes.
> +                */
> +               reg1 = readl(reg);
> +       } else {
> +               /*
> +                * For clocks running below 24MHz, wait a minimum of
> +                * 4 clock cycles.
> +                */
> +               ndelay(4 * (DIV_ROUND_UP(1000000000, rate)));

Can be '1000 * HZ_PER_MHZ'