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Message-ID: <0a18e4ca-cc70-4d91-90af-43319b700e2b@intel.com>
Date: Tue, 15 Oct 2024 20:07:44 -0700
From: Reinette Chatre <reinette.chatre@...el.com>
To: Babu Moger <babu.moger@....com>, <corbet@....net>, <fenghua.yu@...el.com>,
<tglx@...utronix.de>, <mingo@...hat.com>, <bp@...en8.de>,
<dave.hansen@...ux.intel.com>
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<rdunlap@...radead.org>, <tj@...nel.org>, <peterz@...radead.org>,
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Subject: Re: [PATCH v8 06/25] x86/resctrl: Add support to enable/disable AMD
ABMC feature
Hi Babu,
On 10/9/24 10:39 AM, Babu Moger wrote:
> Add the functionality to enable/disable AMD ABMC feature.
>
> AMD ABMC feature is enabled by setting enabled bit(0) in MSR
> L3_QOS_EXT_CFG. When the state of ABMC is changed, the MSR needs
> to be updated on all the logical processors in the QOS Domain.
>
> Hardware counters will reset when ABMC state is changed.
>
> The ABMC feature details are documented in APM listed below [1].
> [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
> Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth
> Monitoring (ABMC).
>
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
> Signed-off-by: Babu Moger <babu.moger@....com>
> ---
With the MSRs ordered numerically per Tony's suggestion:
|Reviewed-by: Reinette Chatre <reinette.chatre@...el.com>
Reinette
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