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Message-ID:
 <CYYPR12MB865575C121660188BDD977B89C462@CYYPR12MB8655.namprd12.prod.outlook.com>
Date: Wed, 16 Oct 2024 04:42:35 +0000
From: "Yuan, Perry" <Perry.Yuan@....com>
To: "Limonciello, Mario" <Mario.Limonciello@....com>, "Shenoy, Gautham Ranjal"
	<gautham.shenoy@....com>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>, "Ugwekar, Dhananjay"
	<Dhananjay.Ugwekar@....com>
Subject: RE: [PATCH 2/4] cpufreq/amd-pstate: Don't update CPPC request in
 amd_pstate_cpu_boost_update()

[AMD Official Use Only - AMD Internal Distribution Only]

Hi Mario,

> -----Original Message-----
> From: Limonciello, Mario <Mario.Limonciello@....com>
> Sent: Sunday, October 13, 2024 1:45 AM
> To: Shenoy, Gautham Ranjal <gautham.shenoy@....com>
> Cc: Yuan, Perry <Perry.Yuan@....com>; linux-kernel@...r.kernel.org; linux-
> pm@...r.kernel.org; Ugwekar, Dhananjay <Dhananjay.Ugwekar@....com>;
> Limonciello, Mario <Mario.Limonciello@....com>
> Subject: [PATCH 2/4] cpufreq/amd-pstate: Don't update CPPC request in
> amd_pstate_cpu_boost_update()
>
> When boost is changed the CPPC value is changed in
> amd_pstate_cpu_boost_update() but then changed again when
> refresh_frequency_limits() and all it's callbacks occur.  The first is a pointless write,
> so instead just update the limits for the policy and let the policy refresh anchor
> everything properly.
>
> Fixes: c8c68c38b56f ("cpufreq: amd-pstate: initialize core precision boost state")
> Signed-off-by: Mario Limonciello <mario.limonciello@....com>
> ---
>  drivers/cpufreq/amd-pstate.c | 24 +-----------------------
>  1 file changed, 1 insertion(+), 23 deletions(-)
>
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index
> dfa9a146769b..13dec8b1e7a8 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -665,34 +665,12 @@ static void amd_pstate_adjust_perf(unsigned int cpu,
> static int amd_pstate_cpu_boost_update(struct cpufreq_policy *policy, bool on)  {
>       struct amd_cpudata *cpudata = policy->driver_data;
> -     struct cppc_perf_ctrls perf_ctrls;
> -     u32 highest_perf, nominal_perf, nominal_freq, max_freq;
> +     u32 nominal_freq, max_freq;
>       int ret = 0;
>
> -     highest_perf = READ_ONCE(cpudata->highest_perf);
> -     nominal_perf = READ_ONCE(cpudata->nominal_perf);
>       nominal_freq = READ_ONCE(cpudata->nominal_freq);
>       max_freq = READ_ONCE(cpudata->max_freq);
>
> -     if (boot_cpu_has(X86_FEATURE_CPPC)) {
> -             u64 value = READ_ONCE(cpudata->cppc_req_cached);
> -
> -             value &= ~GENMASK_ULL(7, 0);
> -             value |= on ? highest_perf : nominal_perf;
> -             WRITE_ONCE(cpudata->cppc_req_cached, value);

The original idea was to update CPU firmware MSR register to limit Frequency from lowlevel,
If the not updating MSR,  could you please check if the boost off can limit the frequency
from power firmware?
If the limitation is working or not needed,  please pick the flag,

Reviewed-by: Perry Yuan <perry.yuan@....com>.


Perry.

> -
> -             wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
> -     } else {
> -             perf_ctrls.max_perf = on ? highest_perf : nominal_perf;
> -             ret = cppc_set_perf(cpudata->cpu, &perf_ctrls);
> -             if (ret) {
> -                     cpufreq_cpu_release(policy);
> -                     pr_debug("Failed to set max perf on CPU:%d. ret:%d\n",
> -                             cpudata->cpu, ret);
> -                     return ret;
> -             }
> -     }
> -
>       if (on)
>               policy->cpuinfo.max_freq = max_freq;
>       else if (policy->cpuinfo.max_freq > nominal_freq * 1000)
> --
> 2.43.0


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