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Message-Id: <20241017143008.983439-1-bwawrzyn@cisco.com>
Date: Thu, 17 Oct 2024 14:30:08 +0000
From: Bartosz Wawrzyniak <bwawrzyn@...co.com>
To: Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
linux-phy@...ts.infradead.org,
linux-kernel@...r.kernel.org
Cc: xe-linux-external@...co.com,
Daniel Walker <danielwa@...co.com>,
Bartosz Stania <sbartosz@...co.com>,
Bartosz Wawrzyniak <bwawrzyn@...co.com>
Subject: [PATCH] phy: cadence: Sierra: Add multilink SGMII + SGMII register configuration
Add multilink SGMII + SGMII register configuration (no SSC) for the
cdns,sierra-phy-t0 compatibility string.
In the case of multilink, when two links are of the same type,
do not enable PLL LC1. Use PLL LC for both links.
Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@...co.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index aeec6eb6be23..c606b281da39 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -1262,12 +1262,18 @@ static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp)
clk_set_rate(sp->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
clk_set_rate(sp->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
- /* PHY configured to use both PLL LC and LC1 */
- regmap_field_write(sp->phy_pll_cfg_1, 0x1);
-
phy_t1 = sp->phys[0].phy_type;
phy_t2 = sp->phys[1].phy_type;
+
+ /*
+ * Configure both PLL LC and LC1 when link types are different.
+ * If both links are of the same type, there is no need to use
+ * a second PLL.
+ */
+ if (phy_t1 != phy_t2)
+ regmap_field_write(sp->phy_pll_cfg_1, 0x1);
+
/*
* PHY configuration for multi-link operation is done in two steps.
* e.g. Consider a case for a 4 lane PHY with PCIe using 2 lanes and QSGMII other 2 lanes.
@@ -2541,6 +2547,9 @@ static const struct cdns_sierra_data cdns_map_sierra = {
[TYPE_NONE] = {
[NO_SSC] = &sgmii_cmn_vals,
},
+ [TYPE_SGMII] = {
+ [NO_SSC] = &sgmii_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
@@ -2582,6 +2591,9 @@ static const struct cdns_sierra_data cdns_map_sierra = {
[TYPE_NONE] = {
[NO_SSC] = &sgmii_pma_ln_vals,
},
+ [TYPE_SGMII] = {
+ [NO_SSC] = &sgmii_pma_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
--
2.28.0
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