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Message-Id: <172917908756.278159.7051019346885032299.b4-ty@kernel.org>
Date: Thu, 17 Oct 2024 21:01:27 +0530
From: Vinod Koul <vkoul@...nel.org>
To: kishon@...nel.org, thomas.richard@...tlin.com,
krzysztof.kozlowski@...aro.org, nichen@...as.ac.cn, rogerq@...nel.org,
c-vankar@...com, t-patil@...com, Siddharth Vadapalli <s-vadapalli@...com>
Cc: linux-phy@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, srk@...com
Subject: Re: [PATCH v3] phy: ti: phy-j721e-wiz: fix usxgmii configuration
On Sat, 12 Oct 2024 11:09:37 +0530, Siddharth Vadapalli wrote:
> Commit b64a85fb8f53 ("phy: ti: phy-j721e-wiz.c: Add usxgmii support in
> wiz driver") added support for USXGMII mode. In doing so, P0_REFCLK_SEL
> was set to "pcs_mac_clk_divx1_ln_0" (0x3) and P0_STANDARD_MODE was set to
> LANE_MODE_GEN1, which results in a data rate of 5.15625 Gbps. However,
> since the USXGMII mode can support up to 10.3125 Gbps data rate, the
> aforementioned fields should be set to "pcs_mac_clk_divx0_ln_0" (0x2) and
> LANE_MODE_GEN2 respectively. The signal corresponding to the USXGMII lane
> of the SERDES has been measured as 5 Gbps without the change and 10 Gbps
> with the change. Hence, fix the configuration accordingly to support
> USXGMII up to 10G.
>
> [...]
Applied, thanks!
[1/1] phy: ti: phy-j721e-wiz: fix usxgmii configuration
commit: b4b32423b6ee6bb96e19fd82bcfd372f6192c737
Best regards,
--
~Vinod
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