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<PAXPR04MB8510814D1AB70634E223887C88472@PAXPR04MB8510.eurprd04.prod.outlook.com>
Date: Thu, 17 Oct 2024 01:31:50 +0000
From: Wei Fang <wei.fang@....com>
To: Marc Kleine-Budde <mkl@...gutronix.de>, Shenwei Wang
<shenwei.wang@....com>, Clark Wang <xiaoning.wang@....com>, "David S. Miller"
<davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski
<kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Richard Cochran
<richardcochran@...il.com>
CC: "imx@...ts.linux.dev" <imx@...ts.linux.dev>, "netdev@...r.kernel.org"
<netdev@...r.kernel.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>, "kernel@...gutronix.de"
<kernel@...gutronix.de>
Subject: RE: [PATCH net-next 01/13] net: fec: fix typos found by codespell
> -----Original Message-----
> From: Marc Kleine-Budde <mkl@...gutronix.de>
> Sent: 2024年10月17日 5:52
> To: Wei Fang <wei.fang@....com>; Shenwei Wang <shenwei.wang@....com>;
> Clark Wang <xiaoning.wang@....com>; David S. Miller
> <davem@...emloft.net>; Eric Dumazet <edumazet@...gle.com>; Jakub
> Kicinski <kuba@...nel.org>; Paolo Abeni <pabeni@...hat.com>; Richard
> Cochran <richardcochran@...il.com>
> Cc: imx@...ts.linux.dev; netdev@...r.kernel.org; linux-kernel@...r.kernel.org;
> kernel@...gutronix.de; Marc Kleine-Budde <mkl@...gutronix.de>
> Subject: [PATCH net-next 01/13] net: fec: fix typos found by codespell
>
> codespell has found some typos in the comments, fix them.
>
> Signed-off-by: Marc Kleine-Budde <mkl@...gutronix.de>
> ---
> drivers/net/ethernet/freescale/fec.h | 8 ++++----
> drivers/net/ethernet/freescale/fec_ptp.c | 4 ++--
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/ethernet/freescale/fec.h
> b/drivers/net/ethernet/freescale/fec.h
> index
> 1cca0425d49397bbdb97f2c058bd759f9e602f17..77c2a08d23542accdb85b37
> a6f86847d9eb56a7a 100644
> --- a/drivers/net/ethernet/freescale/fec.h
> +++ b/drivers/net/ethernet/freescale/fec.h
> @@ -115,7 +115,7 @@
> #define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */
> #define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */
> #define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */
> -#define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */
> +#define IEEE_T_EXCOL 0x260 /* Frames tx'd with excessive collisions */
> #define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun
> */
> #define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */
> #define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */
> @@ -342,7 +342,7 @@ struct bufdesc_ex {
> #define FEC_TX_BD_FTYPE(X) (((X) & 0xf) << 20)
>
> /* The number of Tx and Rx buffers. These are allocated from the page
> - * pool. The code may assume these are power of two, so it it best
> + * pool. The code may assume these are power of two, so it is best
> * to keep them that size.
> * We don't need to allocate pages for the transmitter. We just use
> * the skbuffer directly.
> @@ -460,7 +460,7 @@ struct bufdesc_ex {
> #define FEC_QUIRK_SINGLE_MDIO (1 << 11)
> /* Controller supports RACC register */
> #define FEC_QUIRK_HAS_RACC (1 << 12)
> -/* Controller supports interrupt coalesc */
> +/* Controller supports interrupt coalesce */
> #define FEC_QUIRK_HAS_COALESCE (1 << 13)
> /* Interrupt doesn't wake CPU from deep idle */
> #define FEC_QUIRK_ERR006687 (1 << 14)
> @@ -495,7 +495,7 @@ struct bufdesc_ex {
> */
> #define FEC_QUIRK_HAS_EEE (1 << 20)
>
> -/* i.MX8QM ENET IP version add new feture to generate delayed TXC/RXC
> +/* i.MX8QM ENET IP version add new feature to generate delayed TXC/RXC
> * as an alternative option to make sure it works well with various PHYs.
> * For the implementation of delayed clock, ENET takes synchronized
> 250MHz
> * clocks to generate 2ns delay.
> diff --git a/drivers/net/ethernet/freescale/fec_ptp.c
> b/drivers/net/ethernet/freescale/fec_ptp.c
> index
> 7f6b57432071667e8553363f7c8c21198f38f530..8722f623d9e47e385439f1c
> ee8c677e2b95b236d 100644
> --- a/drivers/net/ethernet/freescale/fec_ptp.c
> +++ b/drivers/net/ethernet/freescale/fec_ptp.c
> @@ -118,7 +118,7 @@ static u64 fec_ptp_read(const struct cyclecounter *cc)
> * @fep: the fec_enet_private structure handle
> * @enable: enable the channel pps output
> *
> - * This function enble the PPS ouput on the timer channel.
> + * This function enable the PPS output on the timer channel.
> */
> static int fec_ptp_enable_pps(struct fec_enet_private *fep, uint enable)
> { @@ -173,7 +173,7 @@ static int fec_ptp_enable_pps(struct
> fec_enet_private *fep, uint enable)
> * very close to the second point, which means NSEC_PER_SEC
> * - ts.tv_nsec is close to be zero(For example 20ns); Since the timer
> * is still running when we calculate the first compare event, it is
> - * possible that the remaining nanoseonds run out before the
> compare
> + * possible that the remaining nanoseconds run out before the
> compare
> * counter is calculated and written into TCCR register. To avoid
> * this possibility, we will set the compare event to be the next
> * of next second. The current setting is 31-bit timer and wrap
>
> --
> 2.45.2
>
It looks good to me, thanks.
Reviewed-by: Wei Fang <wei.fang@....com>
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