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Message-Id: <20241017-sar2130p-clocks-v1-7-f75e740f0a8d@linaro.org>
Date: Thu, 17 Oct 2024 19:56:57 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Taniya Das <quic_tdas@...cinc.com>,
Neil Armstrong <neil.armstrong@...aro.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Konrad Dybcio <konradybcio@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Kalpak Kawadkar <quic_kkawadka@...cinc.com>
Subject: [PATCH 07/14] clk: qcom: clk-branch: Add support for SREG branch
ops
From: Kalpak Kawadkar <quic_kkawadka@...cinc.com>
Add support for SREG branch ops. This is for the clocks which require
additional register operations with the SREG register as a part of
enable / disable operations.
Signed-off-by: Kalpak Kawadkar <quic_kkawadka@...cinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
---
drivers/clk/qcom/clk-branch.c | 32 ++++++++++++++++++++++++++++++++
drivers/clk/qcom/clk-branch.h | 4 ++++
2 files changed, 36 insertions(+)
diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c
index c4c7bd565cc9a3926e24bb12ed6355ec6ddd19fb..9142a33b6b3ba72a7dd9ff80a64c17f2a1746e8c 100644
--- a/drivers/clk/qcom/clk-branch.c
+++ b/drivers/clk/qcom/clk-branch.c
@@ -170,6 +170,31 @@ static void clk_branch2_mem_disable(struct clk_hw *hw)
return clk_branch2_disable(hw);
}
+static int clk_branch2_sreg_enable(struct clk_hw *hw)
+{
+ struct clk_branch *br = to_clk_branch(hw);
+ u32 val;
+ int ret;
+
+ ret = clk_enable_regmap(hw);
+ if (ret)
+ return -EINVAL;
+
+ return regmap_read_poll_timeout(br->clkr.regmap, br->sreg_enable_reg,
+ val, !(val & br->sreg_core_ack_bit), 1, 200);
+}
+
+static void clk_branch2_sreg_disable(struct clk_hw *hw)
+{
+ struct clk_branch *br = to_clk_branch(hw);
+ u32 val;
+
+ clk_disable_regmap(hw);
+
+ regmap_read_poll_timeout(br->clkr.regmap, br->sreg_enable_reg,
+ val, val & br->sreg_periph_ack_bit, 1, 200);
+}
+
const struct clk_ops clk_branch2_mem_ops = {
.enable = clk_branch2_mem_enable,
.disable = clk_branch2_mem_disable,
@@ -203,3 +228,10 @@ const struct clk_ops clk_branch2_prepare_ops = {
.is_prepared = clk_is_enabled_regmap,
};
EXPORT_SYMBOL_GPL(clk_branch2_prepare_ops);
+
+const struct clk_ops clk_branch2_sreg_ops = {
+ .enable = clk_branch2_sreg_enable,
+ .disable = clk_branch2_sreg_disable,
+ .is_enabled = clk_is_enabled_regmap,
+};
+EXPORT_SYMBOL(clk_branch2_sreg_ops);
diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h
index 47bf59a671c3c8516a57c283fce548a6e5f16619..149d04bae25d1a54999e0f938c4fce175a7c3e42 100644
--- a/drivers/clk/qcom/clk-branch.h
+++ b/drivers/clk/qcom/clk-branch.h
@@ -24,8 +24,11 @@
struct clk_branch {
u32 hwcg_reg;
u32 halt_reg;
+ u32 sreg_enable_reg;
u8 hwcg_bit;
u8 halt_bit;
+ u32 sreg_core_ack_bit;
+ u32 sreg_periph_ack_bit;
u8 halt_check;
#define BRANCH_VOTED BIT(7) /* Delay on disable */
#define BRANCH_HALT 0 /* pol: 1 = halt */
@@ -111,6 +114,7 @@ extern const struct clk_ops clk_branch_simple_ops;
extern const struct clk_ops clk_branch2_aon_ops;
extern const struct clk_ops clk_branch2_mem_ops;
extern const struct clk_ops clk_branch2_prepare_ops;
+extern const struct clk_ops clk_branch2_sreg_ops;
#define to_clk_branch(_hw) \
container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
--
2.39.5
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