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Message-ID: <20241017102728.2844274-3-quic_yijiyang@quicinc.com>
Date: Thu, 17 Oct 2024 18:27:25 +0800
From: YijieYang <quic_yijiyang@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio
<konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski
<krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Richard Cochran
<richardcochran@...il.com>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>,
<quic_tingweiz@...cinc.com>, <quic_aiquny@...cinc.com>,
Yijie Yang
<quic_yijiyang@...cinc.com>
Subject: [PATCH v2 2/5] arm64: dts: qcom: qcs8300: add the first 1Gb ethernet
From: Yijie Yang <quic_yijiyang@...cinc.com>
Add the node for the first ethernet interface on qcs8300 platform.
Add the internal SGMII/SerDes PHY node as well.
Signed-off-by: Yijie Yang <quic_yijiyang@...cinc.com>
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 43 +++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 2c35f96c3f28..bf6030d33e56 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -772,6 +772,15 @@ lpass_ag_noc: interconnect@...0000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ serdes0: phy@...9000 {
+ compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy";
+ reg = <0x0 0x8909000 0x0 0xe10>;
+ clocks = <&gcc GCC_SGMI_CLKREF_EN>;
+ clock-names = "sgmi_ref";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
pmu@...1000 {
compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
reg = <0x0 0x9091000 0x0 0x1000>;
@@ -1308,6 +1317,40 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
};
};
+ ethernet0: ethernet@...40000 {
+ compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos";
+ reg = <0x0 0x23040000 0x0 0x10000>,
+ <0x0 0x23056000 0x0 0x100>;
+ reg-names = "stmmaceth", "rgmii";
+
+ interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "sfty";
+
+ clocks = <&gcc GCC_EMAC0_AXI_CLK>,
+ <&gcc GCC_EMAC0_SLV_AHB_CLK>,
+ <&gcc GCC_EMAC0_PTP_CLK>,
+ <&gcc GCC_EMAC0_PHY_AUX_CLK>;
+ clock-names = "stmmaceth",
+ "pclk",
+ "ptp_ref",
+ "phyaux";
+ power-domains = <&gcc GCC_EMAC0_GDSC>;
+
+ phys = <&serdes0>;
+ phy-names = "serdes";
+
+ iommus = <&apps_smmu 0x120 0xf>;
+ dma-coherent;
+
+ snps,tso;
+ snps,pbl = <32>;
+ rx-fifo-depth = <16384>;
+ tx-fifo-depth = <20480>;
+
+ status = "disabled";
+ };
+
nspa_noc: interconnect@...c0000 {
compatible = "qcom,qcs8300-nspa-noc";
reg = <0x0 0x260c0000 0x0 0x16080>;
--
2.34.1
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