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Message-ID: <ZxDqzeA2mz0Ml6cZ@shikoro>
Date: Thu, 17 Oct 2024 12:45:33 +0200
From: Wolfram Sang <wsa+renesas@...g-engineering.com>
To: Claudiu <claudiu.beznea@...on.dev>
Cc: geert+renesas@...der.be, mturquette@...libre.com, sboyd@...nel.org,
robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
alexandre.belloni@...tlin.com, magnus.damm@...il.com,
p.zabel@...gutronix.de, linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-rtc@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Claudiu Beznea <claudiu.beznea.uj@...renesas.com>,
kernel test robot <lkp@...el.com>
Subject: Re: [PATCH v3 06/12] rtc: renesas-rtca3: Add driver for RTCA-3
available on Renesas RZ/G3S SoC
Hi,
sorry for being late to the game. I just noticed this series and
wonder...
> +/* Counter registers. */
> +#define RTCA3_RSECCNT 0x2
> +#define RTCA3_RSECCNT_SEC GENMASK(6, 0)
> +#define RTCA3_RMINCNT 0x4
> +#define RTCA3_RMINCNT_MIN GENMASK(6, 0)
> +#define RTCA3_RHRCNT 0x6
> +#define RTCA3_RHRCNT_HR GENMASK(5, 0)
> +#define RTCA3_RHRCNT_PM BIT(6)
> +#define RTCA3_RWKCNT 0x8
> +#define RTCA3_RWKCNT_WK GENMASK(2, 0)
> +#define RTCA3_RDAYCNT 0xa
> +#define RTCA3_RDAYCNT_DAY GENMASK(5, 0)
> +#define RTCA3_RMONCNT 0xc
> +#define RTCA3_RMONCNT_MONTH GENMASK(4, 0)
> +#define RTCA3_RYRCNT 0xe
> +#define RTCA3_RYRCNT_YEAR GENMASK(7, 0)
... if it has been considered to expand the existing rtc-sh driver? The
register set looks identical up to RMONAR. From that on, it looks a
different. Maybe the different offsets and bit positions could be
abstracted away by some sh_rtc_{read|write} helper? Or is there some
other new handling which makes re-using rtc-sh cumbersome?
Thanks and happy hacking,
Wolfram
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