linux-kernel - [PATCH v2 2/2] usb: dwc3: core: Add support to ignore single SE0 glitches

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Message-ID: <20241017114055.13971-3-quic_uaggarwa@quicinc.com>
Date: Thu, 17 Oct 2024 17:10:55 +0530
From: Uttkarsh Aggarwal <quic_uaggarwa@...cinc.com>
To: Krzysztof Kozlowski <krzk+dt@...nel.org>, Rob Herring <robh@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Greg Kroah-Hartman
	<gregkh@...uxfoundation.org>,
        Felipe Balbi <balbi@...nel.org>,
        Thinh Nguyen
	<Thinh.Nguyen@...opsys.com>
CC: <linux-usb@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <quic_ppratap@...cinc.com>,
        <quic_jackp@...cinc.com>,
        Uttkarsh Aggarwal <quic_uaggarwa@...cinc.com>
Subject: [PATCH v2 2/2] usb: dwc3: core: Add support to ignore single SE0 glitches

Currently in few of Qualcomm chips USB (Low speed) mouse not
detected showing following errors:

  usb 1-1: Device not responding to setup address.
  usb 1-1: device not accepting address 2, error -71
  usb 1-1: new low-speed USB device number 3 using xhci-hcd
  usb 1-1: Device not responding to setup address.
  usb 1-1: Device not responding to setup address.
  usb 1-1: device not accepting address 3, error -71
  usb usb1-port1: attempt power cycle

Based on the Logic analyzer waveforms, It has been identified that there
is skew of about 8nS b/w DP & DM linestate signals (o/p of PHY & i/p to
controller) at the UTMI interface, Due to this controller is seeing SE0
glitch condition, this is causing controller to pre-maturely assume that
PHY has sent all the data & is initiating next packet much early, though
in reality PHY is still busy sending previous packets.

Enabling the GUCTL1.FILTER_SE0_FSLS_EOP bit29 allows the controller to
ignore single SE0 glitches on the linestate during transmission. Only two
or more SE0 signals are recognized as a valid EOP.

When this feature is activated, SE0 signals on the linestate are validated
over two consecutive UTMI/ULPI clock edges for EOP detection.

Device mode (FS): If GUCTL1.FILTER_SE0_FSLS_EOP is set, then for device LPM
handshake, the controller ignores single SE0 glitch on the linestate during
transmit. Only two or more SE0 is considered as a valid EOP on FS port.

Host mode (FS/LS): If GUCTL1.FILTER_SE0_FSLS_EOP is set, then the controller
ignores single SE0 glitch on the linestate during transmit.

Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@...cinc.com>
---
 drivers/usb/dwc3/core.c | 13 +++++++++++++
 drivers/usb/dwc3/core.h |  4 ++++
 2 files changed, 17 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 86b37881aab4..4edd32c44e73 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -222,6 +222,17 @@ static void __dwc3_set_mode(struct work_struct *work)

 	switch (desired_dr_role) {
 	case DWC3_GCTL_PRTCAP_HOST:
+	       /*
+		* Setting GUCTL1 bit 29 so that controller
+		* will ignore single SE0 glitch on the linestate
+		* during transmit.
+		*/
+		if (dwc->filter_se0_fsls_eop_quirk) {
+			reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
+			reg |= DWC3_GUCTL1_FILTER_SE0_FSLS_EOP;
+			dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
+		}
+
 		ret = dwc3_host_init(dwc);
 		if (ret) {
 			dev_err(dwc->dev, "failed to initialize host\n");
@@ -1788,6 +1799,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)

 	dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
 				"snps,tx_de_emphasis_quirk");
+	dwc->filter_se0_fsls_eop_quirk = device_property_read_bool(dev,
+				"snps,filter-se0-fsls-eop-quirk");
 	device_property_read_u8(dev, "snps,tx_de_emphasis",
 				&tx_de_emphasis);
 	device_property_read_string(dev, "snps,hsphy_interface",
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index cc3f32acfaf5..33d53a436fd7 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -276,6 +276,7 @@

 /* Global User Control 1 Register */
 #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT	BIT(31)
+#define DWC3_GUCTL1_FILTER_SE0_FSLS_EOP		BIT(29)
 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
 #define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK	BIT(26)
 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW		BIT(24)
@@ -1140,6 +1141,8 @@ struct dwc3_scratchpad_array {
  * @gfladj_refclk_lpm_sel: set if we need to enable SOF/ITP counter
  *                          running based on ref_clk
  * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
+ * @filter_se0_fsls_eop_quirk: set to ignores single
+ *				SE0 glitch on the linestate during transmit.
  * @tx_de_emphasis: Tx de-emphasis value
  *	0	- -6dB de-emphasis
  *	1	- -3.5dB de-emphasis
@@ -1373,6 +1376,7 @@ struct dwc3 {
 	unsigned		gfladj_refclk_lpm_sel:1;

 	unsigned		tx_de_emphasis_quirk:1;
+	unsigned		filter_se0_fsls_eop_quirk:1;
 	unsigned		tx_de_emphasis:2;

 	unsigned		dis_metastability_quirk:1;
-- 
2.17.1