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Message-ID: <32cf828b-91c8-4710-8943-f2d174ada53b@quicinc.com>
Date: Thu, 17 Oct 2024 17:21:30 +0530
From: Shivnandan Kumar <quic_kshivnan@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>
CC: Sibi Sankar <quic_sibis@...cinc.com>,
Jassi Brar
<jassisinghbrar@...il.com>, Rob Herring <robh@...nel.org>,
"Krzysztof
Kozlowski" <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
<cros-qcom-dts-watchers@...omium.org>,
Konrad Dybcio
<konradybcio@...nel.org>,
<linux-arm-msm@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<devicetree@...r.kernel.org>,
"Ramakrishna
Gottimukkula" <quic_rgottimu@...cinc.com>
Subject: Re: [PATCH 3/3] arm64: dts: qcom: sc7280: Add cpucp mbox node
On 10/6/2024 8:05 AM, Bjorn Andersson wrote:
> On Tue, Sep 24, 2024 at 10:39:41AM GMT, Shivnandan Kumar wrote:
>> Add the CPUCP mailbox node required for communication with CPUCP.
>
> I'd like to see a description of why that's useful...
>
I will add in next patch set.
> But perhaps more importantly, why are there no user(s) of this?
>
We will later add features such as BUS DCVS (memlat algorithm in CPUCP)
and CPUCP logging based on this series.
> Regards,
> Bjorn
>
>>
>> Signed-off-by: Shivnandan Kumar <quic_kshivnan@...cinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 3d8410683402..4b9b26a75c62 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -4009,6 +4009,14 @@ gem_noc: interconnect@...0000 {
>> qcom,bcm-voters = <&apps_bcm_voter>;
>> };
>>
>> + cpucp_mbox: mailbox@...30000 {
>> + compatible = "qcom,sc7280-cpucp-mbox";
>> + reg = <0 0x18590000 0 0x2000>,
>> + <0 0x17C00000 0 0x10>;
>> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> + #mbox-cells = <1>;
>> + };
>> +
>> system-cache-controller@...0000 {
>> compatible = "qcom,sc7280-llcc";
>> reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
>> --
>> 2.25.1
>>
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