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Message-ID: <trinity-c4ba2a12-a350-4681-b2f5-e04c27bb3630-1729264937213@3c-app-gmx-bs21>
Date: Fri, 18 Oct 2024 17:22:17 +0200
From: Frank Wunderlich <frank-w@...lic-files.de>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Cc: Frank Wunderlich <linux@...web.de>, Linus Walleij
<linus.walleij@...aro.org>, Rob Herring <robh@...nel.org>, Krzysztof
Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>, Sean Wang
<sean.wang@...nel.org>, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org,
daniel@...rotopia.org, john@...ozen.org, ansuelsmth@...il.com,
eladwf@...il.com, Sam Shih <sam.shih@...iatek.com>,
Arınç ÜNAL <arinc.unal@...nc9.com>
Subject: Aw: Re: [PATCH v4 2/4] pinctrl: mediatek: add MT7988 pinctrl driver
Hi Angelo
> Gesendet: Donnerstag, 10. Oktober 2024 um 14:28 Uhr
> Betreff: Re: [PATCH v4 2/4] pinctrl: mediatek: add MT7988 pinctrl driver
>
> Il 09/10/24 18:52, Frank Wunderlich ha scritto:
> > From: Daniel Golle <daniel@...rotopia.org>
> >
> > Add pinctrl driver for the MediaTek MT7988 SoC.
> >
> > Signed-off-by: Sam Shih <sam.shih@...iatek.com>
> > Signed-off-by: Daniel Golle <daniel@...rotopia.org>
> > [correctly initialise for the function_desc structure]
> > Signed-off-by: Arınç ÜNAL <arinc.unal@...nc9.com>
> > Signed-off-by: Frank Wunderlich <frank-w@...lic-files.de>
> > ---
> > drivers/pinctrl/mediatek/Kconfig | 7 +
> > drivers/pinctrl/mediatek/Makefile | 1 +
> > drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1526 +++++++++++++++++++++
> > 3 files changed, 1534 insertions(+)
> > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7988.c
> >
> > diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
> > index 7af287252834..952110c783d4 100644
> > --- a/drivers/pinctrl/mediatek/Kconfig
> > +++ b/drivers/pinctrl/mediatek/Kconfig
> > @@ -187,6 +187,13 @@ config PINCTRL_MT7986
> > default ARM64 && ARCH_MEDIATEK
> > select PINCTRL_MTK_MOORE
> >
> > +config PINCTRL_MT7988
> > + bool "Mediatek MT7988 pin control"
> > + depends on OF
> > + depends on ARM64 || COMPILE_TEST
> > + default ARM64 && ARCH_MEDIATEK
> > + select PINCTRL_MTK_MOORE
> > +
> > config PINCTRL_MT8167
> > bool "MediaTek MT8167 pin control"
> > depends on OF
> > diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
> > index 680f7e8526e0..2b47ce030b54 100644
> > --- a/drivers/pinctrl/mediatek/Makefile
> > +++ b/drivers/pinctrl/mediatek/Makefile
> > @@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
> > obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
> > obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
> > obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
> > +obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o
> > obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
> > obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
> > obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
> > diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/drivers/pinctrl/mediatek/pinctrl-mt7988.c
> > new file mode 100644
> > index 000000000000..5479f4fa47a7
> > --- /dev/null
> > +++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c
> > @@ -0,0 +1,1526 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * The MT7988 driver based on Linux generic pinctrl binding.
> > + *
> > + * Copyright (C) 2020 MediaTek Inc.
> > + * Author: Sam Shih <sam.shih@...iatek.com>
> > + */
> > +
> > +#include "pinctrl-moore.h"
> > +
> > +enum MT7988_PINCTRL_REG_PAGE {
>
> Lowercase name for the enumeration, please.
will do in next version
> > + GPIO_BASE,
> > + IOCFG_TR_BASE,
> > + IOCFG_BR_BASE,
> > + IOCFG_RB_BASE,
> > + IOCFG_LB_BASE,
> > + IOCFG_TL_BASE,
> > +};
> > +
>
> ..snip..
>
> > +static const struct mtk_eint_hw mt7988_eint_hw = {
> > + .port_mask = 7,
> > + .ports = 7,
> > + .ap_num = ARRAY_SIZE(mt7988_pins),
> > + .db_cnt = 16,
>
> Are you sure that the EINT controller in this SoC doesn't have the
> DBNC_SET and DBNC_CLR registers?
>
> Another way of asking the same thing: are you sure that this SoC does
> not support interrupt debounce?
Got information from MTK, that hw debounce is only available for pins 0 to 15,
and does not support pins with numbers 16 or higher and definition here is correct.
> > +};
> > +
> > +static const char * const mt7988_pinctrl_register_base_names[] = {
> > + "gpio", "iocfg_tr", "iocfg_br",
> > + "iocfg_rb", "iocfg_lb", "iocfg_tl",
> > +};
> > +
> > +static struct mtk_pin_soc mt7988_data = {
> > + .reg_cal = mt7988_reg_cals,
> > + .pins = mt7988_pins,
> > + .npins = ARRAY_SIZE(mt7988_pins),
> > + .grps = mt7988_groups,
> > + .ngrps = ARRAY_SIZE(mt7988_groups),
> > + .funcs = mt7988_functions,
> > + .nfuncs = ARRAY_SIZE(mt7988_functions),
> > + .eint_hw = &mt7988_eint_hw,
> > + .gpio_m = 0,
> > + .ies_present = false,
> > + .base_names = mt7988_pinctrl_register_base_names,
> > + .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names),
> > + .bias_disable_set = mtk_pinconf_bias_disable_set,
> > + .bias_disable_get = mtk_pinconf_bias_disable_get,
> > + .bias_set = mtk_pinconf_bias_set,
> > + .bias_get = mtk_pinconf_bias_get,
> > + .pull_type = mt7988_pull_type,
> > + .bias_set_combo = mtk_pinconf_bias_set_combo,
> > + .bias_get_combo = mtk_pinconf_bias_get_combo,
> > + .drive_set = mtk_pinconf_drive_set_rev1,
> > + .drive_get = mtk_pinconf_drive_get_rev1,
> > + .adv_pull_get = mtk_pinconf_adv_pull_get,
> > + .adv_pull_set = mtk_pinconf_adv_pull_set,
> > +};
> > +
> > +static const struct of_device_id mt7988_pinctrl_of_match[] = {
>
> Please compress that to a single line.
>
> { .compatible = "mediatek,mt7988-pinctrl" },
will do in next version
> Cheers,
> Angelo
regards Frank
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