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Message-ID: <ZxKQux4I8We0Ax3-@gallifrey>
Date: Fri, 18 Oct 2024 16:45:47 +0000
From: "Dr. David Alan Gilbert" <linux@...blig.org>
To: Borislav Petkov <bp@...en8.de>
Cc: Jens Axboe <axboe@...nel.dk>, Thomas Gleixner <tglx@...utronix.de>,
the arch/x86 maintainers <x86@...nel.org>,
LKML <linux-kernel@...r.kernel.org>,
"regressions@...ts.linux.dev" <regressions@...ts.linux.dev>
Subject: Re: AMD zen microcode updates breaks boot
* Borislav Petkov (bp@...en8.de) wrote:
> On Fri, Oct 18, 2024 at 07:30:15AM -0600, Jens Axboe wrote:
> > At least on mine, the BIOS has an option that says something like "L3
> > cache as numa domain", which is on and why there's 32 nodes on that box.
> > It's pretty handy for testing since there's a crap ton of CPUs, as it
> > makes affinity handling easier.
>
> Right, so two boxes I tested with this:
>
> * 2 socket, a bit different microcode:
>
> [ 22.947525] smp: Brought up 32 nodes, 512 CPUs
>
> * your CPU, one socket:
>
> [ 26.830137] smp: Brought up 16 nodes, 255 CPUs
(Probably unrelated but...)
What happened to number 256 ?
Dave
> [ 37.770789] microcode: Current revision: 0x0aa00215
> [ 37.776231] microcode: Updated early from: 0x0aa00215
>
> and both boot with my debugging patch just fine.
>
> Hmm.
>
> --
> Regards/Gruss,
> Boris.
>
> https://people.kernel.org/tglx/notes-about-netiquette
>
--
-----Open up your eyes, open up your mind, open up your code -------
/ Dr. David Alan Gilbert | Running GNU/Linux | Happy \
\ dave @ treblig.org | | In Hex /
\ _________________________|_____ http://www.treblig.org |_______/
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