[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <320024ab-63af-45eb-a3ae-5486cb2015c0@kernel.dk>
Date: Fri, 18 Oct 2024 10:48:19 -0600
From: Jens Axboe <axboe@...nel.dk>
To: Borislav Petkov <bp@...en8.de>
Cc: Thomas Gleixner <tglx@...utronix.de>,
the arch/x86 maintainers <x86@...nel.org>,
LKML <linux-kernel@...r.kernel.org>,
"regressions@...ts.linux.dev" <regressions@...ts.linux.dev>
Subject: Re: AMD zen microcode updates breaks boot
On 10/18/24 9:51 AM, Borislav Petkov wrote:
> On Fri, Oct 18, 2024 at 07:30:15AM -0600, Jens Axboe wrote:
>> At least on mine, the BIOS has an option that says something like "L3
>> cache as numa domain", which is on and why there's 32 nodes on that box.
>> It's pretty handy for testing since there's a crap ton of CPUs, as it
>> makes affinity handling easier.
>
> Right, so two boxes I tested with this:
>
> * 2 socket, a bit different microcode:
>
> [ 22.947525] smp: Brought up 32 nodes, 512 CPUs
>
> * your CPU, one socket:
>
> [ 26.830137] smp: Brought up 16 nodes, 255 CPUs
> [ 37.770789] microcode: Current revision: 0x0aa00215
> [ 37.776231] microcode: Updated early from: 0x0aa00215
>
> and both boot with my debugging patch just fine.
>
> Hmm.
Funky... Not sure I'll have time to get a serial console on this
thing before next week. Like I mentioned before -rc1, maybe we
revert this change and I'll be happy to test patches as time
permits?
--
Jens Axboe
Powered by blists - more mailing lists