linux-kernel - Re: [PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver

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Message-ID: <20241018-chump-juvenile-dc368d3d2f2c@spud>
Date: Fri, 18 Oct 2024 17:58:44 +0100
From: Conor Dooley <conor@...nel.org>
To: Xu Yilun <yilun.xu@...ux.intel.com>
Cc: iansdannapel@...il.com, mdf@...nel.org, hao.wu@...el.com,
	yilun.xu@...el.com, trix@...hat.com, robh@...nel.org,
	krzk+dt@...nel.org, conor+dt@...nel.org, neil.armstrong@...aro.org,
	heiko.stuebner@...rry.de, rafal@...ecki.pl,
	linus.walleij@...aro.org, linux-fpga@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI
 programming driver

On Fri, Oct 18, 2024 at 09:37:22AM +0800, Xu Yilun wrote:
> On Fri, Sep 27, 2024 at 04:14:42PM +0200, iansdannapel@...il.com wrote:
> > From: Ian Dannapel <iansdannapel@...il.com>
> > 
> > Add a new driver for loading binary firmware to volatile
> > configuration RAM using "SPI passive programming" on Efinix FPGAs.
> > 
> > Signed-off-by: Ian Dannapel <iansdannapel@...il.com>
> > ---
> >  drivers/fpga/Kconfig                    |  10 ++
> >  drivers/fpga/Makefile                   |   1 +
> >  drivers/fpga/efinix-trion-spi-passive.c | 211 ++++++++++++++++++++++++
> >  3 files changed, 222 insertions(+)
> >  create mode 100644 drivers/fpga/efinix-trion-spi-passive.c
> > 
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > index 37b35f58f0df..eb1e44c4e3e0 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -83,6 +83,16 @@ config FPGA_MGR_XILINX_SPI
> >  	  FPGA manager driver support for Xilinx FPGA configuration
> >  	  over slave serial interface.
> >  
> > +config FPGA_MGR_EFINIX_SPI
> > +	tristate "Efinix FPGA configuration over SPI passive"
> > +	depends on SPI
> > +	help
> > +	  This option enables support for the FPGA manager driver to
> > +	  configure Efinix Trion and Titanium Series FPGAs over SPI
> > +	  using passive serial mode.
> > +	  Warning: Do not activate this if there are other SPI devices
> > +	  on the same bus as it might interfere with the transmission.
> 
> Sorry, this won't work. As you can see, the conflict usage of CS causes
> several concerns. Just a text here is far from enough.
> 
> You need to actively work with SPI core/controller drivers to find a
> solution that coordinate the usage of this pin.

Why does it even impact other SPI devices on the bus? It's not /their/
CS line that is being modified here, it is the line for the FPGA's
programming interface, right?
What am I missing here that makes it any different to any other SPI
device that may need it's CS toggled?

Cheers,
Conor.

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