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Message-ID: <20241018130447.GA40439-robh@kernel.org>
Date: Fri, 18 Oct 2024 08:04:47 -0500
From: Rob Herring <robh@...nel.org>
To: Andrew Davis <afd@...com>
Cc: Nishanth Menon <nm@...com>, Vignesh Raghavendra <vigneshr@...com>,
Tero Kristo <kristo@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/5] dt-bindings: soc: ti: ti,j721e-system-controller:
Add PCIe ctrl property
On Wed, Oct 16, 2024 at 06:30:40PM -0500, Andrew Davis wrote:
> Add a pattern property for pcie-ctrl which can be part of this controller.
>
> Signed-off-by: Andrew Davis <afd@...com>
> ---
> .../bindings/soc/ti/ti,j721e-system-controller.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml
> index 378e9cc5fac2a..2a64fc61d1262 100644
> --- a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml
> +++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml
> @@ -68,6 +68,11 @@ patternProperties:
> description:
> The node corresponding to SoC chip identification.
>
> + "^pcie-ctrl@[0-9a-f]+$":
> + type: object
> + description:
> + This is the PCIe control region.
What goes in this node?
> +
> required:
> - compatible
> - reg
> --
> 2.39.2
>
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