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Message-Id: <20241019071037.145314-11-arikalo@gmail.com>
Date: Sat, 19 Oct 2024 09:10:35 +0200
From: Aleksandar Rikalo <arikalo@...il.com>
To: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
Cc: Aleksandar Rikalo <arikalo@...il.com>,
Chao-ying Fu <cfu@...ecomp.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Geert Uytterhoeven <geert@...ux-m68k.org>,
Greg Ungerer <gerg@...nel.org>,
Hauke Mehrtens <hauke@...ke-m.de>,
Ilya Lipnitskiy <ilya.lipnitskiy@...il.com>,
Jiaxun Yang <jiaxun.yang@...goat.com>,
linux-kernel@...r.kernel.org,
linux-mips@...r.kernel.org,
Marc Zyngier <maz@...nel.org>,
Paul Burton <paulburton@...nel.org>,
Peter Zijlstra <peterz@...radead.org>,
Serge Semin <fancer.lancer@...il.com>,
Thomas Gleixner <tglx@...utronix.de>,
Tiezhu Yang <yangtiezhu@...ngson.cn>,
Gregory CLEMENT <gregory.clement@...tlin.com>
Subject: [PATCH v7 10/12] dt-bindings: mips: cpu: Add property for broken HCI information
From: Gregory CLEMENT <gregory.clement@...tlin.com>
Some CM3.5 reports show that Hardware Cache Initialization is
complete, but in reality it's not the case. They also incorrectly
indicate that Hardware Cache Initialization is supported. This
optional property allows warning about this broken feature that cannot
be detected at runtime.
Signed-off-by: Gregory CLEMENT <gregory.clement@...tlin.com>
Signed-off-by: Aleksandar Rikalo <arikalo@...il.com>
---
Documentation/devicetree/bindings/mips/cpus.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml
index a85137add668..57e93c07ab1b 100644
--- a/Documentation/devicetree/bindings/mips/cpus.yaml
+++ b/Documentation/devicetree/bindings/mips/cpus.yaml
@@ -47,6 +47,12 @@ properties:
clocks:
maxItems: 1
+ cm3-l2-config-hci-broken:
+ type: boolean
+ description:
+ If present, indicates that the HCI (Hardware Cache Initialization)
+ information for the L2 cache in multi-cluster configuration is broken.
+
device_type: true
allOf:
--
2.25.1
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