linux-kernel - Re: [PATCH] x86/kvm: Override default caching mode for SEV-SNP and TDX

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Message-ID: <e12a40f6-3323-41bb-867b-ebb37ec57388@redhat.com>
Date: Sun, 20 Oct 2024 13:07:54 +0200
From: Paolo Bonzini <pbonzini@...hat.com>
To: "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
 Vitaly Kuznetsov <vkuznets@...hat.com>, Thomas Gleixner
 <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>,
 Borislav Petkov <bp@...en8.de>, Dave Hansen <dave.hansen@...ux.intel.com>,
 x86@...nel.org, "H. Peter Anvin" <hpa@...or.com>
Cc: kvm@...r.kernel.org, linux-kernel@...r.kernel.org,
 Binbin Wu <binbin.wu@...el.com>, Juergen Gross <jgross@...e.com>,
 Tom Lendacky <thomas.lendacky@....com>
Subject: Re: [PATCH] x86/kvm: Override default caching mode for SEV-SNP and
 TDX

On 10/15/24 11:58, Kirill A. Shutemov wrote:
> AMD SEV-SNP and Intel TDX have limited access to MTRR: either it is not
> advertised in CPUID or it cannot be programmed (on TDX, due to #VE on
> CR0.CD clear).
> 
> This results in guests using uncached mappings where it shouldn't and
> pmd/pud_set_huge() failures due to non-uniform memory type reported by
> mtrr_type_lookup().
> 
> Override MTRR state, making it WB by default as the kernel does for
> Hyper-V guests.
> 
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@...ux.intel.com>
> Suggested-by: Binbin Wu <binbin.wu@...el.com>
> Cc: Juergen Gross <jgross@...e.com>
> Cc: Tom Lendacky <thomas.lendacky@....com>

Queued, thanks.  I'll leave the follow up to the owners of the tip tree.

Paolo

> ---
>   arch/x86/kernel/kvm.c | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
> index 263f8aed4e2c..21e9e4845354 100644
> --- a/arch/x86/kernel/kvm.c
> +++ b/arch/x86/kernel/kvm.c
> @@ -37,6 +37,7 @@
>   #include <asm/apic.h>
>   #include <asm/apicdef.h>
>   #include <asm/hypervisor.h>
> +#include <asm/mtrr.h>
>   #include <asm/tlb.h>
>   #include <asm/cpuidle_haltpoll.h>
>   #include <asm/ptrace.h>
> @@ -980,6 +981,9 @@ static void __init kvm_init_platform(void)
>   	}
>   	kvmclock_init();
>   	x86_platform.apic_post_init = kvm_apic_init;
> +
> +	/* Set WB as the default cache mode for SEV-SNP and TDX */
> +	mtrr_overwrite_state(NULL, 0, MTRR_TYPE_WRBACK);
>   }
>   
>   #if defined(CONFIG_AMD_MEM_ENCRYPT)