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Message-ID: <20241020113351.GAZxTqnz0SOdrMUAA8@fat_crate.local>
Date: Sun, 20 Oct 2024 13:33:51 +0200
From: Borislav Petkov <bp@...en8.de>
To: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: x86-ml <x86@...nel.org>, lkml <linux-kernel@...r.kernel.org>
Subject: [GIT PULL] x86/urgent for v6.12-rc4

Hi Linus,

please pull the x86/urgent lineup for v6.12-rc4.

Thx.

---

The following changes since commit 8cf0b93919e13d1e8d4466eb4080a4c4d9d66d7b:

  Linux 6.12-rc2 (2024-10-06 15:32:27 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip tags/x86_urgent_for_v6.12_rc4

for you to fetch changes up to ffd95846c6ec6cf1f93da411ea10d504036cab42:

  x86/apic: Always explicitly disarm TSC-deadline timer (2024-10-15 05:45:18 -0700)

----------------------------------------------------------------
- Explicitly disable the TSC deadline timer when going idle to address
  some CPU errata in that area

- Do not apply the Zenbleed fix on anything else except AMD Zen2 on the
  late microcode loading path

- Clear CPU buffers later in the NMI exit path on 32-bit to avoid
  register clearing while they still contain sensitive data, for the
  RDFS mitigation

- Do not clobber EFLAGS.ZF with VERW on the opportunistic SYSRET exit
  path on 32-bit

- Fix parsing issues of memory bandwidth specification in sysfs for
  resctrl's memory bandwidth allocation feature

- Other small cleanups and improvements

----------------------------------------------------------------
John Allen (1):
      x86/CPU/AMD: Only apply Zenbleed fix for Zen2 during late microcode load

Martin Kletzander (1):
      x86/resctrl: Avoid overflow in MB settings in bw_validate()

Nathan Chancellor (1):
      x86/resctrl: Annotate get_mem_config() functions as __init

Pawan Gupta (3):
      x86/entry_32: Do not clobber user EFLAGS.ZF
      x86/entry_32: Clear CPU buffers after register restore in NMI return
      x86/bugs: Use code segment selector for VERW operand

Richard Gong (1):
      x86/amd_nb: Add new PCI ID for AMD family 1Ah model 20h

Zhang Rui (1):
      x86/apic: Always explicitly disarm TSC-deadline timer

 arch/x86/entry/entry_32.S                 |  6 ++++--
 arch/x86/include/asm/nospec-branch.h      | 11 ++++++++++-
 arch/x86/kernel/amd_nb.c                  |  2 ++
 arch/x86/kernel/apic/apic.c               | 14 +++++++++++++-
 arch/x86/kernel/cpu/amd.c                 |  3 ++-
 arch/x86/kernel/cpu/resctrl/core.c        |  4 ++--
 arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 23 ++++++++++++++---------
 7 files changed, 47 insertions(+), 16 deletions(-)


-- 
Regards/Gruss,
    Boris.

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