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Message-Id: <20241020194028.2272371-13-l.rubusch@gmail.com>
Date: Sun, 20 Oct 2024 19:40:17 +0000
From: Lothar Rubusch <l.rubusch@...il.com>
To: robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
dinguyen@...nel.org,
marex@...x.de,
s.trumtrar@...gutronix.de
Cc: l.rubusch@...il.com,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCHv2 12/23] ARM: socfpga: dts: add a10 clock binding yaml
Convert content of the altera socfpga.txt to match clock bindings for
the Arria10 SoC devicetrees. Currently all altr,* bindings appear as
error at dtbs_check, since these bindings are only written in .txt
format.
Signed-off-by: Lothar Rubusch <l.rubusch@...il.com>
---
.../bindings/clock/altr,socfpga-a10.yaml | 107 ++++++++++++++++++
1 file changed, 107 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/altr,socfpga-a10.yaml
diff --git a/Documentation/devicetree/bindings/clock/altr,socfpga-a10.yaml b/Documentation/devicetree/bindings/clock/altr,socfpga-a10.yaml
new file mode 100644
index 000000000..795826f53
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/altr,socfpga-a10.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/altr,socfpga-a10.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Device Tree Clock bindings for Altera's SoCFPGA platform
+
+maintainers:
+ - TODO
+
+description:
+ This binding uses the common clock binding[1].
+
+ [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+properties:
+ compatible:
+ description: |
+ shall be one of the following
+ - "altr,socfpga-a10-pll-clock" - for a PLL clock
+ - "altr,socfpga-a10-perip-clk" - The peripheral clock divided from the
+ PLL clock.
+ - "altr,socfpga-a10-gate-clk" - Clocks that directly feed peripherals
+ and can get gated.
+ enum:
+ - altr,socfpga-a10-pll-clock
+ - altr,socfpga-a10-perip-clk
+ - altr,socfpga-a10-gate-clk
+
+ reg:
+ description: |
+ shall be the control register offset from CLOCK_MANAGER's base for the
+ clock.
+ maxItems: 1
+
+ clocks:
+ description: |
+ shall be the input parent clock phandle for the clock. This is either an
+ oscillator or a pll output.
+ minItems: 1
+ maxItems: 5
+
+ '#clock-cells':
+ description: from common clock binding, shall be set to 0.
+ maxItems: 1
+
+ fixed-divider:
+ description: if clocks have a fixed divider value, use this property.
+ minimum: 1
+ maximum: 16
+
+ clk-gate:
+ description: |
+ for "socfpga-a10-gate-clk", clk-gate contains the gating register and the
+ bit index.
+ minItems: 2
+
+ div-reg:
+ description: |
+ for "socfpga-a10-gate-clk" and "socfpga-a10-periph-clk", div-reg contains
+ the divider register, bit shift, and width.
+ minItems: 3
+ maxItems: 3
+
+ clk-phase:
+ description: |
+ for the sdmmc_clk, contains the value of the clock phase that controls
+ the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the
+ second value is the cclk_in_drv(drvsel). The clk-phase is used to enable
+ the correct hold/delay times that is needed for the SD/MMC CIU clock. The
+ values of both can be 0-315 degrees, in 45 degree increments.
+ minItems: 1
+
+required:
+ - compatible
+ - clocks
+ - '#clock-cells'
+
+oneOf:
+ - items:
+ - required:
+ - reg
+ - required:
+ - div-reg
+
+additionalProperties: false
+
+examples:
+ - |
+ main_pll: main_pll@40 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-pll-clock";
+ clocks = <&osc1>, <&cb_intosc_ls_clk>,
+ <&f2s_free_clk>;
+ reg = <0x40>;
+
+ main_noc_base_clk: main_noc_base_clk {
+ compatible = "altr,socfpga-a10-perip-clk";
+ div-reg = <0x140 16 11>;
+ clocks = <&periph_pll>;
+ #clock-cells = <0>;
+ };
+ };
+...
--
2.25.1
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