linux-kernel - Re: [PATCH v3 09/11] PCI: brcmstb: Adjust PHY PLL setup to use a 54MHz input refclk

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Message-ID: <a5a4ce33-3c32-4e43-a39b-7a3514339e37@suse.de>
Date: Mon, 21 Oct 2024 18:39:59 +0300
From: Stanimir Varbanov <svarbanov@...e.de>
To: Jonathan Bell <jonathan@...pberrypi.com>,
 Stanimir Varbanov <svarbanov@...e.de>
Cc: Florian Fainelli <florian.fainelli@...adcom.com>,
 linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-rpi-kernel@...ts.infradead.org,
 linux-pci@...r.kernel.org,
 Broadcom internal kernel review list
 <bcm-kernel-feedback-list@...adcom.com>, Thomas Gleixner
 <tglx@...utronix.de>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Jim Quinlan <jim2101024@...il.com>,
 Nicolas Saenz Julienne <nsaenz@...nel.org>,
 Bjorn Helgaas <bhelgaas@...gle.com>,
 Lorenzo Pieralisi <lpieralisi@...nel.org>, kw@...ux.com,
 Philipp Zabel <p.zabel@...gutronix.de>,
 Andrea della Porta <andrea.porta@...e.com>,
 Phil Elwell <phil@...pberrypi.com>
Subject: Re: [PATCH v3 09/11] PCI: brcmstb: Adjust PHY PLL setup to use a
 54MHz input refclk

Hi,

On 10/21/24 15:56, Jonathan Bell wrote:
> On Thu, 17 Oct 2024 at 15:42, Stanimir Varbanov <svarbanov@...e.de> wrote:
>>
>> Hi Florian,
>>
>> On 10/14/24 20:07, Florian Fainelli wrote:
>>> On 10/14/24 06:07, Stanimir Varbanov wrote:
>>>> Use canned MDIO writes from Broadcom that switch the ref_clk output
>>>> pair to run from the internal fractional PLL, and set the internal
>>>> PLL to expect a 54MHz input reference clock.
>>>>
>>>> Without this RPi5 PCIe cannot enumerate endpoint devices on
>>>> extension connector.
>>>
>>> You could say that the default reference clock for the PLL is 100MHz,
>>> except for some devices, where it is 54MHz, like 2712d0. AFAIR, 2712c1
>>> might have been 100MHz as well, so whether we need to support that
>>> revision of the chip or not might be TBD.
>>
>> I'm confused now, according to [1] :
>>
>> BCM2712C1 - 4GB and 8GB RPi5 models
>> BCM2712D0 - 2GB RPi5 models
>>
>> My device is 4GB RPi5 model so I would expect it is BCM2712C1, thus
>> according to your comment the PLL PHY adjustment is not needed. But I
>> see that the PCIex1 RC cannot enumerate devices on ext PCI connector
>> because of link training failure. Implementing PLL adjustment fixes the
>> failure.
>>
>>
>> ~Stan
>>
>> [1]
>> https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
> 

Thanks for jumping in, Jon.

> The MDIO writes for 2712C1 are required because platform firmware
> arranges for the reference input clock to be 54MHz.
> 2712D0 can't generate a 100MHz reference input, it's 54MHz only. The
> MDIO register defaults are also changed to suit, but there's no harm

I see that MDIO register defaults for pcie2 (where RP1 is connected) are
changed to suit to 54Mhz but this is not true for pcie1 (expansion
connector). And that could explain why the link training is failing on
pcie1.

> in applying the writes anyway.
> Both steppings need to behave identically for compliance and interop reasons.

Yes, for sure.

> RP1 is very tolerant of out-of-spec reference clocks, which is why
> only the expansion connector appears to be affected.

Thank you for clarifications.

~Stan

[1] Firmware version: RPi: BOOTSYS release VERSION:790da7ef DATE:
2024/07/30 TIME: 15:25:46