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Message-Id: <20241021163437.1007507-4-Frank.Li@nxp.com>
Date: Mon, 21 Oct 2024 12:34:35 -0400
From: Frank Li <Frank.Li@....com>
To: shawnguo2@...h.net
Cc: Frank.Li@....com,
conor+dt@...nel.org,
devicetree@...r.kernel.org,
festevam@...il.com,
imx@...ts.linux.dev,
kernel@...gutronix.de,
krzk+dt@...nel.org,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
robh@...nel.org,
s.hauer@...gutronix.de,
shawnguo@...nel.org
Subject: [PATCH v2 4/6] arm64: dts: imx8qxp-mek: add flexcan1 and flexcan2
Add flexcan1 and flexcan2.
Signed-off-by: Frank Li <Frank.Li@....com>
---
change from v1 to v2
- none
---
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 0d14b0def19d4..e9342bf158489 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -57,6 +57,25 @@ reg_audio: regulator-audio {
regulator-name = "cs42888_supply";
};
+ reg_can_en: regulator-can-en {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "can-en";
+ gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_can_stby: regulator-can-stby {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "can-stby";
+ gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_can_en>;
+ };
+
sound-bt-sco {
compatible = "simple-audio-card";
simple-audio-card,bitclock-inversion;
@@ -337,6 +356,20 @@ &cm40_intmux {
status = "okay";
};
+&flexcan1 {
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ pinctrl-names = "default";
+ xceiver-supply = <®_can_stby>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ pinctrl-names = "default";
+ xceiver-supply = <®_can_stby>;
+ status = "okay";
+};
+
&jpegdec {
status = "okay";
};
@@ -567,6 +600,20 @@ IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
>;
};
+ pinctrl_flexcan1: flexcan0grp {
+ fsl,pins = <
+ IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21
+ IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan1grp {
+ fsl,pins = <
+ IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21
+ IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21
+ >;
+ };
+
pinctrl_ioexp_rst: ioexprstgrp {
fsl,pins = <
IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021
--
2.34.1
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