linux-kernel - Re: [PATCH] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Fix X1E80100 resets entries

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Message-ID: <ZxYDwAUNV5Jhar4I@hovoldconsulting.com>
Date: Mon, 21 Oct 2024 09:33:20 +0200
From: Johan Hovold <johan@...nel.org>
To: Abel Vesa <abel.vesa@...aro.org>
Cc: Vinod Koul <vkoul@...nel.org>,
	Kishon Vijay Abraham I <kishon@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Johan Hovold <johan+linaro@...nel.org>,
	Krzysztof Kozlowski <krzk@...nel.org>,
	linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	kernel test robot <lkp@...el.com>
Subject: Re: [PATCH] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Fix
 X1E80100 resets entries

On Fri, Oct 18, 2024 at 04:37:36PM +0300, Abel Vesa wrote:
> The PCIe 6a PHY on X1E80100 uses both resets in 4-lanes mode as well.

Again, this is a bit misleading as PCIe6a is using the
'qcom,x1e80100-qmp-gen4x4-pcie-phy' compatible in both 4-lane and 2-lane
mode even if the original dtsi got this wrong.

PCIe6b will be using 'qcom,x1e80100-qmp-gen4x2-pcie-phy' as that one is
a 2-lane PHY.

Perhaps you can rephrase this so that it doesn't sound like you are
using compatibles to configure PCIe6a?

> So fix the resets entries for it by adding the Gen4 4-lanes compatible
> alongside the 2-lanes one.
> 
> Fixes: 0c5f4d23f776 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x4")
> Reported-by: kernel test robot <lkp@...el.com>
> Closes: https://lore.kernel.org/oe-kbuild-all/202410182029.n2zPkuGx-lkp@intel.com/
> Signed-off-by: Abel Vesa <abel.vesa@...aro.org>

Patch itself looks good.

Johan