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Message-ID: <ZxYQ1FKtloHPnjb_@smile.fi.intel.com>
Date: Mon, 21 Oct 2024 11:29:08 +0300
From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To: Inochi Amaoto <inochiama@...il.com>
Cc: Chen Wang <unicorn_wang@...look.com>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	Jiri Slaby <jirislaby@...nel.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Inochi Amaoto <inochiama@...look.com>, Yixun Lan <dlan@...too.org>,
	linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org,
	devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v2 2/2] serial: 8250_dw: Add Sophgo SG2044 quirk

On Mon, Oct 21, 2024 at 03:26:06PM +0800, Inochi Amaoto wrote:
> SG2044 relys on an internal divisor when calculating bitrate, which
> means a wrong clock for the most common bitrates. So add a quirk for
> this uart device to skip the set rate call and only relys on the
> internal UART divisor.

Assuming DT bindings are okay,
Reviewed-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>

-- 
With Best Regards,
Andy Shevchenko



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