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Message-ID: <ZxYYCvwTn5V2cw3m@hovoldconsulting.com>
Date: Mon, 21 Oct 2024 10:59:54 +0200
From: Johan Hovold <johan@...nel.org>
To: Abel Vesa <abel.vesa@...aro.org>
Cc: Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Johan Hovold <johan+linaro@...nel.org>,
Krzysztof Kozlowski <krzk@...nel.org>,
linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
kernel test robot <lkp@...el.com>
Subject: Re: [PATCH] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Fix
X1E80100 resets entries
On Mon, Oct 21, 2024 at 11:53:31AM +0300, Abel Vesa wrote:
> On 24-10-21 09:33:20, Johan Hovold wrote:
> > On Fri, Oct 18, 2024 at 04:37:36PM +0300, Abel Vesa wrote:
> > > The PCIe 6a PHY on X1E80100 uses both resets in 4-lanes mode as well.
> >
> > Again, this is a bit misleading as PCIe6a is using the
> > 'qcom,x1e80100-qmp-gen4x4-pcie-phy' compatible in both 4-lane and 2-lane
> > mode even if the original dtsi got this wrong.
>
> But the lane config within the phy driver differs based on the
> compatible.
No, it differs based on the value of the TCSR register.
> > PCIe6b will be using 'qcom,x1e80100-qmp-gen4x2-pcie-phy' as that one is
> > a 2-lane PHY.
>
> Wouldn't the PCIe6a also have to switch to gen4x2 compatible on a board
> where PCIe6b is used?
Nope, it stays the same (e.g. as the hardware block is the same).
> > Perhaps you can rephrase this so that it doesn't sound like you are
> > using compatibles to configure PCIe6a?
>
> But currently we do configure PCIe6a based on compatibles.
>
> What am I missing ?
No, as we've discussed in multiple threads already:
https://lore.kernel.org/all/ZwPDxd9JJbgDeJTi@hovoldconsulting.com/
https://lore.kernel.org/lkml/ZtG2dUVkdwBpBbix@hovoldconsulting.com/
Johan
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