linux-kernel - Re: [PATCH v5 3/3] riscv: dts: starfive: add DeepComputing FML13V01 board device tree

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <c048d270-7a07-4807-b816-0f4e0aeb67f7@kernel.org>
Date: Mon, 21 Oct 2024 14:47:32 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Conor Dooley <conor@...nel.org>
Cc: Guodong Xu <guodong@...cstar.com>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Emil Renner Berthing <kernel@...il.dk>, rafal@...ecki.pl,
 Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
 Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt
 <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
 Neil Armstrong <neil.armstrong@...aro.org>,
 Heiko Stuebner <heiko.stuebner@...rry.de>,
 Michael Zhu <michael.zhu@...rfivetech.com>,
 Drew Fustini <drew@...gleboard.org>, Alexandru Stan <ams@...me.work>,
 Daniel Schaefer <dhs@...me.work>, Sandie Cao <sandie.cao@...pcomputing.io>,
 Yuning Liang <yuning.liang@...pcomputing.io>,
 Huiming Qiu <huiming.qiu@...pcomputing.io>, Alex Elder <elder@...cstar.com>,
 linux@...me.work, devicetree@...r.kernel.org,
 linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 3/3] riscv: dts: starfive: add DeepComputing FML13V01
 board device tree

On 21/10/2024 13:16, Conor Dooley wrote:
> On Mon, Oct 21, 2024 at 09:17:59AM +0200, Krzysztof Kozlowski wrote:
>> On Sun, Oct 20, 2024 at 09:49:59PM +0800, Guodong Xu wrote:
>>> From: Sandie Cao <sandie.cao@...pcomputing.io>
>>> +&camss {
>>> +	status = "disabled";
>>> +};
>>> +
>>> +&csi2rx {
>>> +	status = "disabled";
>>> +};
> 
> You can drop these two, I marked them disabled in the common file
> earlier this week.
> 1
>>> +
>>> +&gmac0 {
>>> +	status = "disabled";
>>> +};
>>> +
>>> +&i2c0 {
>>> +	status = "disabled";
>>> +};
>>> +
>>> +&pwm {
>>> +	status = "disabled";
>>> +};
>>> +
>>> +&pwmdac {
>>> +	status = "disabled";
>>> +};
>>> +
>>> +&spi0 {
>>> +	status = "disabled";
>>
>> If your board has to disable all these, then they should not have been
>> enabled in DTSI in the first place. Only blocks present and working in
>> the SoC (without amny external needs) should be enabled.
>>
>> I suggest to fix that aspect first.
> 
> Eh, I don't think I agree. Having 5 disables here is a lesser evil than
> reproducing 90% of jh7110-common.dtsi or shunting a bunch of stuff
> around. Emil?

Why reproducing 90%? Only enable would be here, no? Or you want to say
the common DTSI has things which do not exist?

Best regards,
Krzysztof