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Message-ID: <20241022172059.wuw5xel7m4vobarq@thinkpad>
Date: Tue, 22 Oct 2024 22:50:59 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: Richard Zhu <hongxing.zhu@....com>
Cc: kw@...ux.com, bhelgaas@...gle.com, lpieralisi@...nel.org,
frank.li@....com, l.stach@...gutronix.de, robh+dt@...nel.org,
conor+dt@...nel.org, shawnguo@...nel.org,
krzysztof.kozlowski+dt@...aro.org, festevam@...il.com,
s.hauer@...gutronix.de, linux-pci@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, kernel@...gutronix.de,
imx@...ts.linux.dev
Subject: Re: [PATCH v4 9/9] arm64: dts: imx95: Add ref clock for i.MX95 PCIe
On Tue, Oct 15, 2024 at 04:33:33PM +0800, Richard Zhu wrote:
> Add ref clock for i.MX95 PCIe.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> Reviewed-by: Frank Li <Frank.Li@....com>
> ---
> arch/arm64/boot/dts/freescale/imx95.dtsi | 18 ++++++++++++++----
> 1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 03661e76550f..5cb504b5f851 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -1473,6 +1473,14 @@ smmu: iommu@...d0000 {
> };
> };
>
> + hsio_blk_ctl: syscon@...100c0 {
> + compatible = "nxp,imx95-hsio-blk-ctl", "syscon";
> + reg = <0x0 0x4c0100c0 0x0 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dummy>;
> + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> + };
This is an internal reference clock, right? Please mention it in patch
description since the controller supports external reference clock also.
- Mani
> +
> pcie0: pcie@...00000 {
> compatible = "fsl,imx95-pcie";
> reg = <0 0x4c300000 0 0x10000>,
> @@ -1500,8 +1508,9 @@ pcie0: pcie@...00000 {
> clocks = <&scmi_clk IMX95_CLK_HSIO>,
> <&scmi_clk IMX95_CLK_HSIOPLL>,
> <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
> + <&hsio_blk_ctl 0>;
> + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
> assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> <&scmi_clk IMX95_CLK_HSIOPLL>,
> <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> @@ -1528,8 +1537,9 @@ pcie0_ep: pcie-ep@...00000 {
> clocks = <&scmi_clk IMX95_CLK_HSIO>,
> <&scmi_clk IMX95_CLK_HSIOPLL>,
> <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
> + <&hsio_blk_ctl 0>;
> + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
> assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> <&scmi_clk IMX95_CLK_HSIOPLL>,
> <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> --
> 2.37.1
>
--
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