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Message-ID: <c0784c5e-fc71-64c5-e09f-63e1abd1b61d@ti.com>
Date: Tue, 22 Oct 2024 11:55:25 +0530
From: Devarsh Thakkar <devarsht@...com>
To: Aradhya Bhatia <aradhya.bhatia@...ux.dev>,
Tomi Valkeinen
<tomi.valkeinen@...asonboard.com>,
Dmitry Baryshkov
<dmitry.baryshkov@...aro.org>,
Laurent Pinchart
<laurent.pinchart@...asonboard.com>,
Andrzej Hajda <andrzej.hajda@...el.com>,
Neil Armstrong <neil.armstrong@...aro.org>,
Robert Foss <rfoss@...nel.org>, Jonas Karlman <jonas@...boo.se>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard
<mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
David Airlie
<airlied@...il.com>, Simona Vetter <simona@...ll.ch>
CC: Dominik Haller <d.haller@...tec.de>, Sam Ravnborg <sam@...nborg.org>,
Kieran Bingham <kieran.bingham+renesas@...asonboard.com>,
Nishanth Menon
<nm@...com>, Vignesh Raghavendra <vigneshr@...com>,
Praneeth Bajjuri
<praneeth@...com>, Udit Kumar <u-kumar1@...com>,
Jayesh Choudhary
<j-choudhary@...com>,
DRI Development List <dri-devel@...ts.freedesktop.org>,
Linux Kernel List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 07/13] drm/bridge: cdns-dsi: Wait for Clk and Data
Lanes to be ready
Hi Aradhya,
Thanks for the patch.
On 20/10/24 01:24, Aradhya Bhatia wrote:
> From: Aradhya Bhatia <a-bhatia1@...com>
[...]
> + /*
> + * Now that the DSI Link and DSI Phy are initialized,
> + * wait for the CLK and Data Lanes to be ready.
> + */
> + tmp = CLK_LANE_RDY;
> + for (int i = 0; i < nlanes; i++)
> + tmp |= DATA_LANE_RDY(i);
> +
> + if (readl_poll_timeout(dsi->regs + MCTL_MAIN_STS, status,
> + status & tmp, 100, 500000))
The above would mark the condition as true even if one data lane gets ready. I
think we need to poll until all data lanes are marked as ready. Also good to
give a warning in case we time out.
IMHO below should fix this:
WARN_ON_ONCE(readl_poll_timeout(dsi->regs + MCTL_MAIN_STS, status,
(tmp == (status & tmp)), 100, 0));
Regards
Devarsh
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