linux-kernel - Re: [PATCH v2 08/11] clk: qcom: add support for GCC on SAR2130P

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Message-ID: <ec0f2cb4-1461-4eef-a441-d61cbe02804d@quicinc.com>
Date: Tue, 22 Oct 2024 12:40:50 +0530
From: Taniya Das <quic_tdas@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
        Bjorn Andersson
	<andersson@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        "Stephen
 Boyd" <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski
	<krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Neil Armstrong
	<neil.armstrong@...aro.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        "Konrad
 Dybcio" <konradybcio@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        Kalpak Kawadkar
	<quic_kkawadka@...cinc.com>
Subject: Re: [PATCH v2 08/11] clk: qcom: add support for GCC on SAR2130P



On 10/21/2024 4:00 PM, Dmitry Baryshkov wrote:
> Add driver for the Global Clock Controller as present on the Qualcomm
> SAR2130P platform. This is based on the msm-5.10 tree, tag
> KERNEL.PLATFORM.1.0.r4-00400-NEO.0.
> 
> Co-developed-by: Kalpak Kawadkar <quic_kkawadka@...cinc.com>
> Signed-off-by: Kalpak Kawadkar <quic_kkawadka@...cinc.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> ---
>   drivers/clk/qcom/Kconfig        |    9 +
>   drivers/clk/qcom/Makefile       |    1 +
>   drivers/clk/qcom/gcc-sar2130p.c | 2326 +++++++++++++++++++++++++++++++++++++++
>   3 files changed, 2336 insertions(+)
> 
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index e5d7c89b0dab6b4fc7133d8e348ae61d38f91770..5f7bf9db76cfcef1ab18a6ba09fb4dc506695f9d 100644
> --- a/drivers/clk/qcom/Kconfig

> +
> +static struct gdsc pcie_0_gdsc = {
> +	.gdscr = 0x7b004,
> +	.collapse_ctrl = 0x62200,
> +	.collapse_mask = BIT(0),
> +	.pd = {
> +		.name = "pcie_0_gdsc",
> +	},
> +	.pwrsts = PWRSTS_OFF_ON,
> +	.flags = VOTABLE | RETAIN_FF_ENABLE,
> +};
> +
> +static struct gdsc pcie_0_phy_gdsc = {
> +	.gdscr = 0x7c000,
> +	.collapse_ctrl = 0x62200,
> +	.collapse_mask = BIT(3),
> +	.pd = {
> +		.name = "pcie_0_phy_gdsc",
> +	},
> +	.pwrsts = PWRSTS_OFF_ON,
> +	.flags = VOTABLE | RETAIN_FF_ENABLE,
> +};
> +
> +static struct gdsc pcie_1_gdsc = {
> +	.gdscr = 0x9d004,
> +	.collapse_ctrl = 0x62200,
> +	.collapse_mask = BIT(1),
> +	.pd = {
> +		.name = "pcie_1_gdsc",
> +	},
> +	.pwrsts = PWRSTS_OFF_ON,
> +	.flags = VOTABLE | RETAIN_FF_ENABLE,
> +};
> +
> +static struct gdsc pcie_1_phy_gdsc = {
> +	.gdscr = 0x9e000,
> +	.collapse_ctrl = 0x62200,
> +	.collapse_mask = BIT(4),
> +	.pd = {
> +		.name = "pcie_1_phy_gdsc",
> +	},
> +	.pwrsts = PWRSTS_OFF_ON,
> +	.flags = VOTABLE | RETAIN_FF_ENABLE,
> +};
> +
> +static struct gdsc usb30_prim_gdsc = {
> +	.gdscr = 0x49004,
> +	.pd = {
> +		.name = "usb30_prim_gdsc",
> +	},
> +	.pwrsts = PWRSTS_OFF_ON,
> +	.flags = RETAIN_FF_ENABLE,
> +};
> +
> +static struct gdsc usb3_phy_gdsc = {
> +	.gdscr = 0x60018,
> +	.pd = {
> +		.name = "usb3_phy_gdsc",
> +	},
> +	.pwrsts = PWRSTS_OFF_ON,
> +	.flags = RETAIN_FF_ENABLE,
> +};
> +
Dimtry, could you also add,
"hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"
static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_hf0_gdsc = {
         .gdscr = 0x8d204,
         .pd = {
                 .name = "hlos1_vote_mm_snoc_mmu_tbu_hf0_gdsc",
         },
         .pwrsts = PWRSTS_OFF_ON,
         .flags = VOTABLE,
};

"hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc"   --> 0x8d054
"hlos1_vote_turing_mmu_tbu0_gdsc"   --> 0x8d05c	
"hlos1_vote_turing_mmu_tbu1_gdsc"   --> 0x8d060	



-- 
Thanks & Regards,
Taniya Das.